src/soc/mediatek/mt8173/rtc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <delay.h>
  16 #include <soc/rtc_common.h>
  17 #include <soc/rtc.h>
  18 #include <soc/mt6391.h>
  19 #include <soc/pmic_wrap.h>
  20 #include <types.h>
  21
  22 #define RTC_GPIO_USER_MASK        ((1 << 13) - (1 << 8))
  23
  24
  25 /* initialize rtc related gpio */
  26 static int rtc_gpio_init(void)
  27 {
  28         u16 con;
  29
  30         mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE,
  31                                 MT6391_GPIO_PULL_DOWN);  /* RTC_32K1V8 */
  32
  33         /* Export 32K clock RTC_32K2V8 */
  34         rtc_read(RTC_CON, &con);
  35         con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN);
  36         con |= (RTC_CON_GPEN | RTC_CON_GOE);
  37         con &= ~(RTC_CON_F32KOB);
  38         rtc_write(RTC_CON, con);
  39         return rtc_write_trigger();
  40 }
  41
  42 /* set xosc mode */
  43 void rtc_osc_init(void)
  44 {
  45         u16 con;
  46
  47         /* enable 32K export */
  48         rtc_gpio_init();
  49
  50         rtc_write(PMIC_RG_TOP_CKTST2, 0x0);
  51         rtc_read(RTC_OSC32CON, &con);
  52         if ((con & 0x1f) != 0x0)        /* check XOSCCALI */
  53                 rtc_xosc_write(0x3);
  54 }
  55
  56 /* low power detect setting */
  57 static int rtc_lpd_init(void)
  58 {
  59         pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
  60         if (!rtc_write_trigger())
  61                 return 0;
  62
  63         pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0);
  64         if (!rtc_write_trigger())
  65                 return 0;
  66
  67         pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0);
  68         if (!rtc_write_trigger())
  69                 return 0;
  70
  71         return 1;
  72 }
  73
  74 /* rtc init check */
  75 int rtc_init(u8 recover)
  76 {
  77         int ret;
  78
  79         rtc_info("recovery: %d\n", recover);
  80
  81         if (!rtc_writeif_unlock()) {
  82                 ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
  83                 goto err;
  84         }
  85
  86         if (!rtc_gpio_init()) {
  87                 ret = -RTC_STATUS_GPIO_INIT_FAIL;
  88                 goto err;
  89         }
  90
  91         /* Use SW to detect 32K mode instead of HW */
  92         if (recover)
  93                 pwrap_write_field(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
  94
  95         if (!rtc_xosc_write(0x3)) {
  96                 ret = -RTC_STATUS_OSC_SETTING_FAIL;
  97                 goto err;
  98         }
  99
 100         if (recover)
 101                 mdelay(1000);
 102
 103         /* write powerkeys */
 104         rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
 105         rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
 106         if (!rtc_write_trigger()) {
 107                 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
 108                 goto err;
 109         }
 110
 111         if (recover)
 112                 pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
 113
 114         if (!rtc_xosc_write(0)) {
 115                 ret = -RTC_STATUS_OSC_SETTING_FAIL;
 116                 goto err;
 117         }
 118
 119         if (!rtc_reg_init()) {
 120                 ret = -RTC_STATUS_REG_INIT_FAIL;
 121                 goto err;
 122         }
 123
 124         if (!rtc_lpd_init()) {
 125                 ret = -RTC_STATUS_LPD_INIT_FAIL;
 126                 goto err;
 127         }
 128
 129         return RTC_STATUS_OK;
 130 err:
 131         rtc_info("init fail: ret=%d\n", ret);
 132         return ret;
 133 }
 134
 135 /* enable rtc bbpu */
 136 static void rtc_bbpu_power_on(void)
 137 {
 138         u16 bbpu;
 139         int ret;
 140
 141         /* pull PWRBB high */
 142         bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN;
 143         rtc_write(RTC_BBPU, bbpu);
 144         ret = rtc_write_trigger();
 145         rtc_info("rtc_write_trigger=%d\n", ret);
 146
 147         /* enable DCXO to transform external 32KHz clock to 26MHz clock
 148            directly sent to SoC */
 149         pwrap_write_field(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
 150         pwrap_write_field(PMIC_RG_DCXO_POR2_CON3,
 151                      BIT(8) | BIT(9) | BIT(10) | BIT(11), 0, 0);
 152         pwrap_write_field(PMIC_RG_DCXO_CON2,
 153                      BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0);
 154
 155         rtc_read(RTC_BBPU, &bbpu);
 156         rtc_info("done BBPU=%#x\n", bbpu);
 157
 158         /* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */
 159         pwrap_write_field(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
 160 }
 161
 162 /* the rtc boot flow entry */
 163 void rtc_boot(void)
 164 {
 165         rtc_write(PMIC_RG_TOP_CKPDN, 0);
 166         rtc_write(PMIC_RG_TOP_CKPDN2, 0);
 167
 168         rtc_boot_common();
 169         rtc_bbpu_power_on();
 170 }