src/soc/mediatek/mt8173/mt6391.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <assert.h>
  15 #include <console/console.h>
  16 #include <delay.h>
  17 #include <soc/addressmap.h>
  18 #include <soc/mt6391.h>
  19 #include <soc/pmic_wrap.h>
  20 #include <types.h>
  21
  22 #if CONFIG(DEBUG_PMIC)
  23 #define DEBUG_PMIC(level, x...)         printk(level, x)
  24 #else
  25 #define DEBUG_PMIC(level, x...)
  26 #endif
  27
  28 int mt6391_configure_ca53_voltage(int uv)
  29 {
  30         /* target voltage = 700mv + 6.25mv * buck_val */
  31         u16 buck_val = (uv - 700000) / 6250;
  32         u16 current_val = pwrap_read_field(PMIC_RG_VCA15_CON12, 0x7f, 0x0);
  33
  34         assert(buck_val < (1 << 8));
  35         pwrap_write_field(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
  36         pwrap_write_field(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
  37
  38         /* For buck delay, default slew rate is 6.25mv/0.5us */
  39         if (buck_val > current_val)
  40                 return ((buck_val - current_val) / 2) ;
  41         else
  42                 return 0;
  43 }
  44
  45 static void mt6391_configure_vcama(enum ldo_voltage vsel)
  46 {
  47         /* 2'b00: 1.5V
  48          * 2'b01: 1.8V
  49          * 2'b10: 2.5V
  50          * 2'b11: 2.8V
  51          */
  52         pwrap_write_field(PMIC_RG_ANALDO_CON6, vsel - 2,
  53                           PMIC_RG_VCAMA_VOSEL_MASK, PMIC_RG_VCAMA_VOSEL_SHIFT);
  54         pwrap_write_field(PMIC_RG_ANALDO_CON2, 1,
  55                           PMIC_RG_VCAMA_EN_MASK, PMIC_RG_VCAMA_EN_SHIFT);
  56 }
  57
  58 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
  59 {
  60         u16 addr;
  61         switch (ldo) {
  62         case LDO_VCAMD:
  63                 assert(vsel != 0);
  64                 if (vsel == LDO_1P22)
  65                         vsel = 0;
  66                 break;
  67         case LDO_VGP2:
  68                 assert(vsel != 1);
  69                 if (vsel == LDO_1P0)
  70                         vsel = 1;
  71                 break;
  72         case LDO_VGP5:
  73                 assert(vsel != 7);
  74                 if (vsel == LDO_2P0)
  75                         vsel = 7;
  76                 break;
  77         case LDO_VCAMA:
  78                 assert(vsel > LDO_1P3 && vsel < LDO_3P0);
  79                 mt6391_configure_vcama(vsel);
  80                 return;
  81         default:
  82                 break;
  83         }
  84         assert(vsel < LDO_NUM_VOLTAGES);
  85
  86         if (ldo == LDO_VGP6)
  87                 addr = PMIC_RG_DIGLDO_CON33;
  88         else
  89                 addr = PMIC_RG_DIGLDO_CON19 + ldo * 2;
  90
  91         pwrap_write_field(addr, vsel, 0x7, 5);
  92         pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
  93
  94 }
  95
  96 void mt6391_enable_reset_when_ap_resets(void)
  97 {
  98         /* Enable AP watchdog reset */
  99         pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0);
 100 }
 101
 102 static void mt6391_init_setting(void)
 103 {
 104         /* Enable PMIC RST function (depends on main chip RST function) */
 105         /*
 106          * state1: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=1, RG_RST_PART_SEL=1
 107          * state2: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=0, RG_RST_PART_SEL=1
 108          * state3: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=x, RG_RST_PART_SEL=0
 109          */
 110         pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1);
 111         pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2);
 112         pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4);
 113
 114         /* Disable AP watchdog reset */
 115         pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0);
 116
 117         /* Enable CA15 by default for different PMIC behavior */
 118         pwrap_write_field(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0);
 119         pwrap_write_field(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0);
 120         pwrap_write_field(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0);
 121         udelay(200);  /* delay for Buck ready */
 122
 123         /* [3:3]: RG_PWMOC_CK_PDN; For OC protection */
 124         pwrap_write_field(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3);
 125         /* [9:9]: RG_SRCVOLT_HW_AUTO_EN; */
 126         pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9);
 127         /* [8:8]: RG_OSC_SEL_AUTO; */
 128         pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8);
 129         /* [6:6]: RG_SMPS_DIV2_SRC_AUTOFF_DIS; */
 130         pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6);
 131         /* [5:5]: RG_SMPS_AUTOFF_DIS; */
 132         pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5);
 133         /* [7:7]: VDRM_DEG_EN; */
 134         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7);
 135         /* [6:6]: VSRMCA7_DEG_EN; */
 136         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6);
 137         /* [5:5]: VPCA7_DEG_EN; */
 138         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5);
 139         /* [4:4]: VIO18_DEG_EN; */
 140         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4);
 141         /* [3:3]: VGPU_DEG_EN; For OC protection */
 142         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3);
 143         /* [2:2]: VCORE_DEG_EN; */
 144         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2);
 145         /* [1:1]: VSRMCA15_DEG_EN; */
 146         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1);
 147         /* [0:0]: VCA15_DEG_EN; */
 148         pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0);
 149         /* [11:11]: RG_INT_EN_THR_H; */
 150         pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 11);
 151         /* [10:10]: RG_INT_EN_THR_L; */
 152         pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 10);
 153         /* [4:4]: RG_INT_EN_BAT_L; */
 154         pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 4);
 155         /* [11:11]: RG_INT_EN_VGPU; OC protection */
 156         pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 11);
 157         /* [8:8]: RG_INT_EN_VCA15; OC protection */
 158         pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 8);
 159         /* [12:0]: BUCK_RSV; for OC protection */
 160         pwrap_write_field(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0);
 161         /* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */
 162         pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 10);
 163         /* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */
 164         pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6);
 165         /* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */
 166         pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4);
 167         /* [3:2]: QI_VPCA7_VSLEEP; sleep mode only (0.85V) */
 168         pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2);
 169         /* [1:0]: QI_VCA15_VSLEEP; sleep mode only (0.7V) */
 170         pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0);
 171         /* [13:12]: RG_VCA15_CSL2; for OC protection */
 172         pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12);
 173         /* [11:10]: RG_VCA15_CSL1; for OC protection */
 174         pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10);
 175         /* [15:15]: VCA15_SFCHG_REN; soft change rising enable */
 176         pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15);
 177         /* [14:8]: VCA15_SFCHG_RRATE; soft change rising step=0.5 */
 178         pwrap_write_field(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8);
 179         /* [7:7]: VCA15_SFCHG_FEN; soft change falling enable */
 180         pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7);
 181         /* [6:0]: VCA15_SFCHG_FRATE; soft change falling step=2us */
 182         pwrap_write_field(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0);
 183         /* [6:0]: VCA15_VOSEL_SLEEP; sleep mode only (0.7V) */
 184         pwrap_write_field(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0);
 185         /* [8:8]: VCA15_VSLEEP_EN; set sleep mode reference volt */
 186         pwrap_write_field(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8);
 187         /* [5:4]: VCA15_VOSEL_TRANS_EN; rising & falling enable */
 188         pwrap_write_field(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4);
 189         /* [5:5]: VSRMCA15_TRACK_SLEEP_CTRL; */
 190         pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5);
 191         /* [5:4]: VSRMCA15_VOSEL_SEL; */
 192         pwrap_write_field(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4);
 193         /* [15:15]: VSRMCA15_SFCHG_REN; */
 194         pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15);
 195         /* [14:8]: VSRMCA15_SFCHG_RRATE; */
 196         pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8);
 197         /* [7:7]: VSRMCA15_SFCHG_FEN; */
 198         pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7);
 199         /* [6:0]: VSRMCA15_SFCHG_FRATE; */
 200         pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0);
 201         /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */
 202         pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0);
 203         /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */
 204         pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8);
 205         /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */
 206         pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4);
 207         /* [1:1]: VCORE_VOSEL_CTRL; sleep mode voltage control fo */
 208         pwrap_write_field(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1);
 209         /* [5:4]: VCORE_VOSEL_SEL; */
 210         pwrap_write_field(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4);
 211         /* [15:15]: VCORE_SFCHG_REN; */
 212         pwrap_write_field(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15);
 213         /* [14:8]: VCORE_SFCHG_RRATE; */
 214         pwrap_write_field(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8);
 215         /* [6:0]: VCORE_SFCHG_FRATE; */
 216         pwrap_write_field(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0);
 217         /* [6:0]: VCORE_VOSEL_SLEEP; Sleep mode setting only (0. */
 218         pwrap_write_field(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0);
 219         /* [8:8]: VCORE_VSLEEP_EN; Sleep mode HW control  R2R to */
 220         pwrap_write_field(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8);
 221         /* [5:4]: VCORE_VOSEL_TRANS_EN; Follows MT6320 VCORE set */
 222         pwrap_write_field(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4);
 223         /* [1:0]: VCORE_TRANSTD; */
 224         pwrap_write_field(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0);
 225         /* [9:8]: RG_VGPU_CSL; for OC protection */
 226         pwrap_write_field(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8);
 227         /* [15:15]: VGPU_SFCHG_REN; */
 228         pwrap_write_field(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15);
 229         /* [14:8]: VGPU_SFCHG_RRATE; */
 230         pwrap_write_field(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8);
 231         /* [6:0]: VGPU_SFCHG_FRATE; */
 232         pwrap_write_field(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0);
 233         /* [5:4]: VGPU_VOSEL_TRANS_EN; */
 234         pwrap_write_field(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4);
 235         /* [1:0]: VGPU_TRANSTD; */
 236         pwrap_write_field(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0);
 237         /* [5:4]: VPCA7_VOSEL_SEL; */
 238         pwrap_write_field(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4);
 239         /* [15:15]: VPCA7_SFCHG_REN; */
 240         pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15);
 241         /* [14:8]: VPCA7_SFCHG_RRATE; */
 242         pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8);
 243         /* [7:7]: VPCA7_SFCHG_FEN; */
 244         pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7);
 245         /* [6:0]: VPCA7_SFCHG_FRATE; */
 246         pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0);
 247         /* [6:0]: VPCA7_VOSEL_SLEEP; */
 248         pwrap_write_field(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0);
 249         /* [8:8]: VPCA7_VSLEEP_EN; */
 250         pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8);
 251         /* [5:4]: VPCA7_VOSEL_TRANS_EN; */
 252         pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4);
 253         /* [5:5]: VSRMCA7_TRACK_SLEEP_CTRL; */
 254         pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5);
 255         /* [5:4]: VSRMCA7_VOSEL_SEL; */
 256         pwrap_write_field(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4);
 257         /* [15:15]: VSRMCA7_SFCHG_REN; */
 258         pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15);
 259         /* [14:8]: VSRMCA7_SFCHG_RRATE; */
 260         pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8);
 261         /* [7:7]: VSRMCA7_SFCHG_FEN; */
 262         pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7);
 263         /* [6:0]: VSRMCA7_SFCHG_FRATE; */
 264         pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0);
 265         /* [6:0]: VSRMCA7_VOSEL_SLEEP; */
 266         pwrap_write_field(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0);
 267         /* [8:8]: VSRMCA7_VSLEEP_EN; */
 268         pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8);
 269         /* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */
 270         pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4);
 271         /* [8:8]: VDRM_VSLEEP_EN; */
 272         pwrap_write_field(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8);
 273         /* [2:2]: VIBR_THER_SHEN_EN; */
 274         pwrap_write_field(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2);
 275         /* [5:5]: THR_HWPDN_EN; */
 276         pwrap_write_field(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5);
 277         /* [3:3]: RG_RST_DRVSEL; */
 278         pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3);
 279         /* [2:2]: RG_EN_DRVSEL; */
 280         pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2);
 281         /* [1:1]: PWRBB_DEB_EN; */
 282         pwrap_write_field(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1);
 283         /* [12:12]: VSRMCA15_PG_H2L_EN; */
 284         pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12);
 285         /* [11:11]: VPCA15_PG_H2L_EN; */
 286         pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11);
 287         /* [10:10]: VCORE_PG_H2L_EN; */
 288         pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10);
 289         /* [9:9]: VSRMCA7_PG_H2L_EN; */
 290         pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9);
 291         /* [8:8]: VPCA7_PG_H2L_EN; */
 292         pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8);
 293         /* [1:1]: STRUP_PWROFF_PREOFF_EN; */
 294         pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1);
 295         /* [0:0]: STRUP_PWROFF_SEQ_EN; */
 296         pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0);
 297         /* [15:8]: RG_ADC_TRIM_CH_SEL; */
 298         pwrap_write_field(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8);
 299         /* [1:1]: FLASH_THER_SHDN_EN; */
 300         pwrap_write_field(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1);
 301         /* [1:1]: KPLED_THER_SHDN_EN; */
 302         pwrap_write_field(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1);
 303         /* [14:8]: VSRMCA15_VOSEL_OFFSET; set offset=100mV */
 304         pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8);
 305         /* [6:0]: VSRMCA15_VOSEL_DELTA; set delta=0mV */
 306         pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0);
 307         /* [14:8]: VSRMCA15_VOSEL_ON_HB; set HB=1.15V */
 308         pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8);
 309         /* [6:0]: VSRMCA15_VOSEL_ON_LB; set LB=0.7V */
 310         pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0);
 311         /* [6:0]: VSRMCA15_VOSEL_SLEEP_LB; set sleep LB=0.7V */
 312         pwrap_write_field(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0);
 313         /* [14:8]: VSRMCA7_VOSEL_OFFSET; set offset=25mV */
 314         pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8);
 315         /* [6:0]: VSRMCA7_VOSEL_DELTA; set delta=0mV */
 316         pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0);
 317         /* [14:8]: VSRMCA7_VOSEL_ON_HB; set HB=1.275V */
 318         pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8);
 319         /* [6:0]: VSRMCA7_VOSEL_ON_LB; set LB=1.05000V */
 320         pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0);
 321         /* [6:0]: VSRMCA7_VOSEL_SLEEP_LB; set sleep LB=0.85000 */
 322         pwrap_write_field(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0);
 323         /* [1:1]: VCA15_VOSEL_CTRL, VCA15_EN_CTRL; DVS HW control */
 324         pwrap_write_field(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0);
 325         /* [1:1]: VSRMCA15_VOSEL_CTRL, VSRAM15_EN_CTRL; */
 326         pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0);
 327         /* [1:1]: VPCA7_VOSEL_CTRL; */
 328         pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1);
 329         /* [1:1]: VSRMCA7_VOSEL_CTRL; */
 330         pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1);
 331         /* [0:0]: VSRMCA7_EN_CTRL; */
 332         pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0);
 333         /* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */
 334         pwrap_write_field(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4);
 335         /* [4:4]: VSRMCA15_TRACK_ON_CTRL; */
 336         pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4);
 337         /* [4:4]: VPCA7_TRACK_ON_CTRL; */
 338         pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4);
 339         /* [4:4]: VSRMCA7_TRACK_ON_CTRL; */
 340         pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4);
 341         /* [15:14]: VGPU OC; */
 342         pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 14);
 343         /* [3:2]: VCA15 OC; */
 344         pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 2);
 345
 346         /* Set VPCA7 to 1.2V */
 347         pwrap_write_field(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0);
 348         pwrap_write_field(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0);
 349         /* Set VSRMCA7 to 1.1V */
 350         pwrap_write_field(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0);
 351         pwrap_write_field(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0);
 352
 353         /* Enable VGP6 and set to 3.3V*/
 354         pwrap_write_field(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15);
 355         pwrap_write_field(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5);
 356
 357         /* Set VDRM to 1.21875V */
 358         pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0);
 359         pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
 360
 361         /* 26M clock amplitude adjust */
 362         pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2);
 363         pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
 364
 365         /* For low power, set VTCXO switch by SRCVOLTEN */
 366         pwrap_write_field(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0);
 367         /* [6:5]=0(VTCXO_SRCLK_MODE_SEL) */
 368         pwrap_write_field(PMIC_RG_ANALDO_CON0, 0, 0x3, 13);
 369         /* [11]=0(VTCXO_ON_CTRL), */
 370         pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 11);
 371         /* [10]=1(RG_VTCXO_EN), */
 372         pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 10);
 373         /* [4:3]=1(RG_VTCXOTD_SEL) */
 374         pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
 375         /* For low power, VIO18 set sleep_en to HW mode */
 376         pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
 377
 378 }
 379
 380 static void mt6391_default_buck_voltage(void)
 381 {
 382         u16 reg = 0;
 383         u16 buck = 0;
 384         /*
 385          * There are two kinds of PMIC used for MT8173 : MT6397s/MT6391.
 386          *
 387          * MT6397s: the default voltage of register was not suitable for
 388          * MT8173, needs to apply the setting of eFuse.
 389          * VPCA15/VSRMCA15/: 1.15V
 390          * VCORE: 1.05V
 391          *
 392          * MT6391: the default voltage of register was matched for MT8173.
 393          * VPAC15/VCORE/VGPU: 1.0V
 394          * VSRMCA15: 1.0125V
 395          */
 396         reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0);
 397
 398         if ((reg & 0x01) == 0x01) {
 399                 /* VCORE */
 400                 reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12);
 401                 buck = pwrap_read_field(PMIC_RG_VCORE_CON9, 0x7f, 0x0);
 402
 403                 /* VCORE_VOSEL[3:6] => eFuse bit 268-271 */
 404                 buck = (buck & 0x07) | (reg << 3);
 405                 pwrap_write_field(PMIC_RG_VCORE_CON9, buck, 0x7f, 0x0);
 406                 pwrap_write_field(PMIC_RG_VCORE_CON10, buck, 0x7f, 0x0);
 407
 408                 reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0);
 409                 /* VCA15 */
 410                 buck = 0;
 411                 buck = pwrap_read_field(PMIC_RG_VCA15_CON9, 0x7f, 0x0);
 412                 buck = (buck & 0x07) | ((reg & 0x0F) << 3);
 413                 pwrap_write_field(PMIC_RG_VCA15_CON9, buck, 0x7f, 0x0);
 414                 pwrap_write_field(PMIC_RG_VCA15_CON10, buck, 0x7f, 0x0);
 415
 416                 /* VSAMRCA15 */
 417                 buck = 0;
 418                 buck = pwrap_read_field(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0);
 419                 buck = (buck & 0x07) | ((reg & 0xF0) >> 1);
 420                 pwrap_write_field(PMIC_RG_VSRMCA15_CON9, buck, 0x7f, 0x0);
 421                 pwrap_write_field(PMIC_RG_VSRMCA15_CON10, buck, 0x7f, 0x0);
 422
 423                 /* set the power control by register(use original) */
 424                 pwrap_write_field(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12);
 425         }
 426 }
 427
 428 void mt6391_init(void)
 429 {
 430         if (pwrap_init())
 431                 die("ERROR - Failed to initialize pmic wrap!");
 432         /* pmic initial setting */
 433         mt6391_init_setting();
 434
 435         /* Adjust default BUCK voltage from eFuse */
 436         mt6391_default_buck_voltage();
 437 }
 438
 439 /* API of GPIO in PMIC MT6391 */
 440 enum {
 441         MAX_GPIO_REG_BITS = 16,
 442         MAX_GPIO_MODE_PER_REG = 5,
 443         GPIO_MODE_BITS = 3,
 444         GPIO_PORT_OFFSET = 3,
 445         GPIO_SET_OFFSET = 2,
 446         GPIO_RST_OFFSET = 4,
 447         MAX_MT6391_GPIO = 40
 448 };
 449
 450 enum {
 451         MT6391_GPIO_DIRECTION_IN = 0,
 452         MT6391_GPIO_DIRECTION_OUT = 1,
 453 };
 454
 455 enum {
 456         MT6391_GPIO_MODE = 0,
 457 };
 458
 459 static void pos_bit_calc(u32 pin, u16 *pos, u16 *bit)
 460 {
 461         *pos = (pin / MAX_GPIO_REG_BITS) << GPIO_PORT_OFFSET;
 462         *bit = pin % MAX_GPIO_REG_BITS;
 463 }
 464
 465 static void pos_bit_calc_mode(u32 pin, u16 *pos, u16 *bit)
 466 {
 467         *pos = (pin / MAX_GPIO_MODE_PER_REG) << GPIO_PORT_OFFSET;
 468         *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
 469 }
 470
 471 static s32 mt6391_gpio_set_dir(u32 pin, u32 dir)
 472 {
 473         u16 pos;
 474         u16 bit;
 475         u16 reg;
 476
 477         assert(pin <= MAX_MT6391_GPIO);
 478
 479         pos_bit_calc(pin, &pos, &bit);
 480
 481         if (dir == MT6391_GPIO_DIRECTION_IN)
 482                 reg = MT6391_GPIO_DIR_BASE + pos + GPIO_RST_OFFSET;
 483         else
 484                 reg = MT6391_GPIO_DIR_BASE + pos + GPIO_SET_OFFSET;
 485
 486         if (pwrap_write(reg, 1L << bit) != 0)
 487                 return -1;
 488
 489         return 0;
 490 }
 491
 492 void mt6391_gpio_set_pull(u32 pin, enum mt6391_pull_enable enable,
 493                           enum mt6391_pull_select select)
 494 {
 495         u16 pos;
 496         u16 bit;
 497         u16 en_reg, sel_reg;
 498
 499         assert(pin <= MAX_MT6391_GPIO);
 500
 501         pos_bit_calc(pin, &pos, &bit);
 502
 503         if (enable == MT6391_GPIO_PULL_DISABLE) {
 504                 en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_RST_OFFSET;
 505         } else {
 506                 en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_SET_OFFSET;
 507                 sel_reg = (select == MT6391_GPIO_PULL_DOWN) ?
 508                           (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_RST_OFFSET) :
 509                           (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_SET_OFFSET);
 510                 pwrap_write(sel_reg, 1L << bit);
 511         }
 512         pwrap_write(en_reg, 1L << bit);
 513 }
 514
 515 int mt6391_gpio_get(u32 pin)
 516 {
 517         u16 pos;
 518         u16 bit;
 519         u16 reg;
 520         u16 data;
 521
 522         assert(pin <= MAX_MT6391_GPIO);
 523
 524         pos_bit_calc(pin, &pos, &bit);
 525
 526         reg = MT6391_GPIO_DIN_BASE + pos;
 527         pwrap_read(reg, &data);
 528
 529         return (data & (1L << bit)) ? 1 : 0;
 530 }
 531
 532 void mt6391_gpio_set(u32 pin, int output)
 533 {
 534         u16 pos;
 535         u16 bit;
 536         u16 reg;
 537
 538         assert(pin <= MAX_MT6391_GPIO);
 539
 540         pos_bit_calc(pin, &pos, &bit);
 541
 542         if (output == 0)
 543                 reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_RST_OFFSET;
 544         else
 545                 reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_SET_OFFSET;
 546
 547         pwrap_write(reg, 1L << bit);
 548 }
 549
 550 void mt6391_gpio_set_mode(u32 pin, int mode)
 551 {
 552         u16 pos;
 553         u16 bit;
 554         u16 mask = (1L << GPIO_MODE_BITS) - 1;
 555
 556         assert(pin <= MAX_MT6391_GPIO);
 557
 558         pos_bit_calc_mode(pin, &pos, &bit);
 559         pwrap_write_field(MT6391_GPIO_MODE_BASE + pos, mode, mask, bit);
 560 }
 561
 562 void mt6391_gpio_input_pulldown(u32 gpio)
 563 {
 564         mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE,
 565                              MT6391_GPIO_PULL_DOWN);
 566         mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
 567         mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
 568 }
 569
 570 void mt6391_gpio_input_pullup(u32 gpio)
 571 {
 572         mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE,
 573                              MT6391_GPIO_PULL_UP);
 574         mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
 575         mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
 576 }
 577
 578 void mt6391_gpio_input(u32 gpio)
 579 {
 580         mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE,
 581                              MT6391_GPIO_PULL_DOWN);
 582         mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
 583         mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
 584 }
 585
 586 void mt6391_gpio_output(u32 gpio, int value)
 587 {
 588         mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE,
 589                              MT6391_GPIO_PULL_DOWN);
 590         mt6391_gpio_set(gpio, value);
 591         mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_OUT);
 592         mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
 593 }