src/soc/mediatek/mt8173/include/soc/emi.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef SOC_MEDIATEK_MT8173_EMI_H
  16 #define SOC_MEDIATEK_MT8173_EMI_H
  17
  18 #include <soc/dramc_common.h>
  19 #include <stdint.h>
  20 #include <types.h>
  21
  22 /* DDR type */
  23 enum ram_type {
  24         TYPE_INVALID,
  25         TYPE_DDR1,
  26         TYPE_LPDDR2,
  27         TYPE_LPDDR3,
  28         TYPE_PCDDR3
  29 };
  30
  31 enum {
  32         /*
  33          * Vmem voltage adjustment:
  34          * 1) HV: high voltage
  35          * 2) NV: normal voltage
  36          * 3) LV: low voltage
  37          */
  38         Vmem_HV_LPDDR3 = 0x50,  /* 1.300V */
  39         Vmem_NV_LPDDR3 = 0x44,  /* 1.225V */
  40         Vmem_LV_LPDDR3 = 0x36   /* 1.138V */
  41 };
  42
  43 enum {
  44         /*
  45          * Vcore voltage adjustment:
  46          * 1) HHV: extra high voltage
  47          * 2) HV: high voltage
  48          * 3) NV: normal voltage
  49          * 4) LV: low voltage
  50          * 5) LLV: extra low voltage
  51          */
  52         Vcore_HHV_LPPDR3 = 0x60,   /* 1.300V */
  53         Vcore_HV_LPPDR3  = 0x48,   /* 1.150V */
  54         Vcore_NV_LPPDR3  = 0x44,   /* 1.125V */
  55         Vcore_LV_LPPDR3  = 0x34,   /* 1.025V */
  56         Vcore_LLV_LPPDR3 = 0x25    /* 0.931V */
  57 };
  58
  59 struct mt8173_calib_params {
  60         u8 impedance_drvp;
  61         u8 impedance_drvn;
  62         u8 datlat_ucfirst;
  63         s8 ca_train[CHANNEL_NUM][CATRAINING_NUM];
  64         s8 ca_train_center[CHANNEL_NUM];
  65         s8 wr_level[CHANNEL_NUM][DQS_NUMBER];
  66         u8 gating_win[CHANNEL_NUM][DUAL_RANKS][GW_PARAM_NUM];
  67         u32 rx_dqs_dly[CHANNEL_NUM];
  68         u32 rx_dq_dly[CHANNEL_NUM][DQS_BIT_NUMBER];
  69 };
  70
  71 struct mt8173_timing_params {
  72         u32 actim;
  73         u32 actim1;
  74         u32 actim05t;
  75         u32 conf1;
  76         u32 conf2;
  77         u32 ddr2ctl;
  78         u32 gddr3ctl1;
  79         u32 misctl0;
  80         u32 pd_ctrl;
  81         u32 rkcfg;
  82         u32 test2_4;
  83         u32 test2_3;
  84 };
  85
  86 struct mt8173_emi_params {
  87         u32 cona;
  88         u32 conb;
  89         u32 conc;
  90         u32 cond;
  91         u32 cone;
  92         u32 conf;
  93         u32 cong;
  94         u32 conh;
  95         u32 conm_1;
  96         u32 conm_2;
  97         u32 mdct_1;
  98         u32 mdct_2;
  99         u32 test0;
 100         u32 test1;
 101         u32 testb;
 102         u32 testc;
 103         u32 testd;
 104         u32 arba;
 105         u32 arbc;
 106         u32 arbd;
 107         u32 arbe;
 108         u32 arbf;
 109         u32 arbg;
 110         u32 arbi;
 111         u32 arbj;
 112         u32 arbk;
 113         u32 slct_1;
 114         u32 slct_2;
 115         u32 bmen;
 116 };
 117
 118 struct mt8173_mrs_params {
 119         u32 mrs_1;
 120         u32 mrs_2;
 121         u32 mrs_3;
 122         u32 mrs_10;
 123         u32 mrs_11;
 124         u32 mrs_63;
 125 };
 126
 127 enum {
 128         /* CONA = 0x000 */
 129         CONA_DUAL_CH_EN  = BIT(0),
 130         CONA_32BIT_EN  = BIT(1),
 131         CONA_DUAL_RANK_EN  = BIT(17),
 132         COL_ADDR_BITS_SHIFT = 4,
 133         COL_ADDR_BITS_MASK = 3 << COL_ADDR_BITS_SHIFT,
 134         ROW_ADDR_BITS_SHIFT = 12,
 135         ROW_ADDR_BITS_MASK = 3 << ROW_ADDR_BITS_SHIFT
 136 };
 137
 138 struct mt8173_sdram_params {
 139         struct mt8173_calib_params calib_params;
 140         struct mt8173_timing_params ac_timing;
 141         struct mt8173_emi_params emi_set;
 142         struct mt8173_mrs_params mrs_set;
 143         enum ram_type type;
 144         unsigned int dram_freq;
 145 };
 146
 147 int complex_mem_test(u8 *start, unsigned int len);
 148 void mt_set_emi(const struct mt8173_sdram_params *sdram_params);
 149 void mt_mem_init(const struct mt8173_sdram_params *sdram_params);
 150 const struct mt8173_sdram_params *get_sdram_config(void);
 151 size_t sdram_size(void);
 152 #endif