src/soc/mediatek/mt8173/dsi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <assert.h>
  16 #include <device/mmio.h>
  17 #include <console/console.h>
  18 #include <delay.h>
  19 #include <soc/dsi.h>
  20 #include <timer.h>
  21
  22 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
  23 {
  24         u32 txdiv0, txdiv1;
  25         u64 pcw;
  26         u32 reg;
  27         int i;
  28
  29         reg = read32(&mipi_tx0->dsi_bg_con);
  30
  31         reg = (reg & (~RG_DSI_V02_SEL)) | (4 << 20);
  32         reg = (reg & (~RG_DSI_V032_SEL)) | (4 << 17);
  33         reg = (reg & (~RG_DSI_V04_SEL)) | (4 << 14);
  34         reg = (reg & (~RG_DSI_V072_SEL)) | (4 << 11);
  35         reg = (reg & (~RG_DSI_V10_SEL)) | (4 << 8);
  36         reg = (reg & (~RG_DSI_V12_SEL)) | (4 << 5);
  37         reg |= RG_DSI_BG_CKEN;
  38         reg |= RG_DSI_BG_CORE_EN;
  39         write32(&mipi_tx0->dsi_bg_con, reg);
  40         udelay(30);
  41
  42         clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE,
  43                      8 << 4 | RG_DSI_LNT_HS_BIAS_EN);
  44
  45         setbits32(&mipi_tx0->dsi_con,
  46                   RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN);
  47
  48         clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN,
  49                      RG_DSI_MPPLL_SDM_PWR_ON);
  50
  51         clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
  52
  53         if (data_rate > 500 * MHz) {
  54                 txdiv0 = 0;
  55                 txdiv1 = 0;
  56         } else if (data_rate >= 250 * MHz) {
  57                 txdiv0 = 1;
  58                 txdiv1 = 0;
  59         } else if (data_rate >= 125 * MHz) {
  60                 txdiv0 = 2;
  61                 txdiv1 = 0;
  62         } else if (data_rate >= 62 * MHz) {
  63                 txdiv0 = 2;
  64                 txdiv1 = 1;
  65         } else {
  66                 /* MIN = 50 */
  67                 assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
  68                 txdiv0 = 2;
  69                 txdiv1 = 2;
  70         }
  71
  72         clrsetbits32(&mipi_tx0->dsi_pll_con0,
  73                      RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 |
  74                      RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3);
  75
  76         /**
  77          * PLL PCW config
  78          * PCW bit 24~30 = integer part of pcw
  79          * PCW bit 0~23 = fractional part of pcw
  80          * pcw = data_Rate*4*txdiv/(Ref_clk*2);
  81          * Post DIV =4, so need data_Rate*4
  82          * Ref_clk is 26MHz
  83          */
  84         pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24;
  85         pcw /= 13 * MHz;
  86         write32(&mipi_tx0->dsi_pll_con2, pcw);
  87
  88         setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);
  89
  90         setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN);
  91
  92         for (i = 0; i < lanes; i++)
  93                 setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN);
  94
  95         setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
  96
  97         udelay(40);
  98
  99         clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
 100         clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
 101 }
 102
 103 void mtk_dsi_reset(void)
 104 {
 105         setbits32(&dsi0->dsi_con_ctrl, 3);
 106         clrbits32(&dsi0->dsi_con_ctrl, 1);
 107 }
 108
 109 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
 110 {
 111         int lpx = 5;
 112         timing->lpx = lpx;
 113         timing->da_hs_prepare = 6;
 114         timing->da_hs_zero = 10;
 115         timing->da_hs_trail = 8;
 116
 117         timing->ta_go = 4 * lpx;
 118         timing->ta_sure = 3 * lpx / 2;
 119         timing->ta_get = 5 * lpx;
 120         timing->da_hs_exit = 7;
 121
 122         timing->da_hs_sync = 0;
 123         timing->clk_hs_exit = 2 * lpx;
 124
 125         timing->d_phy = 12;
 126 }
 127
 128 void mtk_dsi_pin_drv_ctrl(void)
 129 {
 130         struct stopwatch sw;
 131         uint32_t pwr_ack;
 132
 133         setbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
 134
 135         stopwatch_init_usecs_expire(&sw, 1000);
 136
 137         do {
 138                 if (stopwatch_expired(&sw)) {
 139                         printk(BIOS_ERR, "enable lvdstx_power failed!!!\n");
 140                         return;
 141                 }
 142                 pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK;
 143         } while (pwr_ack == 0);
 144
 145         clrbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
 146 }