src/soc/intel/xeon_sp/lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <arch/ioapic.h>
  18 #include <intelblocks/lpc_lib.h>
  19 #include <soc/soc_util.h>
  20 #include <soc/iomap.h>
  21
  22 static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
  23         { 0, 0 }
  24 };
  25
  26 const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
  27 {
  28         return xeon_lpc_fixed_mmio_ranges;
  29 }
  30
  31 void lpc_soc_init(struct device *dev)
  32 {
  33         printk(BIOS_SPEW, "pch: lpc_init\n");
  34
  35         /* FSP configures IOAPIC and PCHInterrupt Config */
  36         printk(BIOS_SPEW, "IOAPICID 0x%x, 0x%x\n",
  37                 io_apic_read((void *)IO_APIC_ADDR, 0x00),
  38                 ((io_apic_read((void *)IO_APIC_ADDR, 0x00) & 0x0f000000) >> 24));
  39 }
  40
  41 void pch_lpc_soc_fill_io_resources(struct device *dev)
  42 {
  43 }