src/soc/intel/xeon_sp/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #ifndef _SOC_CHIP_H_
  18 #define _SOC_CHIP_H_
  19
  20 #include <stdint.h>
  21 #include <intelblocks/cfg.h>
  22 #include <soc/irq.h>
  23
  24 struct soc_intel_xeon_sp_config {
  25         /* Common struct containing soc config data required by common code */
  26         struct soc_intel_common_config common_soc_config;
  27
  28         /**
  29          * Interrupt Routing configuration
  30          * If bit7 is 1, the interrupt is disabled.
  31          */
  32         uint8_t pirqa_routing;
  33         uint8_t pirqb_routing;
  34         uint8_t pirqc_routing;
  35         uint8_t pirqd_routing;
  36         uint8_t pirqe_routing;
  37         uint8_t pirqf_routing;
  38         uint8_t pirqg_routing;
  39         uint8_t pirqh_routing;
  40
  41         /**
  42          * Device Interrupt Routing configuration
  43          * Interrupt Pin x Route.
  44          * 0h = PIRQA#
  45          * 1h = PIRQB#
  46          * 2h = PIRQC#
  47          * 3h = PIRQD#
  48          * 4h = PIRQE#
  49          * 5h = PIRQF#
  50          * 6h = PIRQG#
  51          * 7h = PIRQH#
  52          */
  53         uint16_t ir00_routing;
  54         uint16_t ir01_routing;
  55         uint16_t ir02_routing;
  56         uint16_t ir03_routing;
  57         uint16_t ir04_routing;
  58
  59         /**
  60         * Device Interrupt Polarity Control
  61         * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  62         * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  63         * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  64         * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  65         */
  66         uint32_t ipc0;
  67         uint32_t ipc1;
  68         uint32_t ipc2;
  69         uint32_t ipc3;
  70
  71         uint64_t turbo_ratio_limit;
  72         uint64_t turbo_ratio_limit_cores;
  73
  74         uint32_t pstate_req_ratio;
  75
  76         uint32_t vtd_support;
  77         uint32_t coherency_support;
  78         uint32_t ats_support;
  79 };
  80
  81 extern struct chip_operations soc_intel_xeon_sp_ops;
  82
  83 typedef struct soc_intel_xeon_sp_config config_t;
  84
  85 #endif