soc: Remove copyright notices
[coreboot.git] / src / soc / intel / xeon_sp / bootblock / bootblock.c
blob6b2c48809dc71a8d1c7568c63b9a070c324f0c98
1 /*
2 * This file is part of the coreboot project.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <bootblock_common.h>
17 #include <device/pci.h>
18 #include <FsptUpd.h>
19 #include <intelblocks/fast_spi.h>
20 #include <soc/iomap.h>
21 #include <console/console.h>
23 const FSPT_UPD temp_ram_init_params = {
24 .FspUpdHeader = {
25 .Signature = FSPT_UPD_SIGNATURE,
26 .Revision = 1,
27 .Reserved = {0},
29 .FsptCoreUpd = {
30 .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
31 .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
32 .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
33 .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
34 .Reserved1 = {0},
36 .FsptConfig = {
37 .PcdFsptPort80RouteDisable = 0,
38 .ReservedTempRamInitUpd = {0},
40 .UnusedUpdSpace0 = {0},
41 .UpdTerminator = 0x55AA,
44 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
46 fast_spi_cache_bios_region();
48 bootblock_main_with_basetime(base_timestamp);
51 void bootblock_soc_early_init(void)
53 fast_spi_early_init(SPI_BASE_ADDRESS);
56 void bootblock_soc_init(void)
58 if (CONFIG(BOOTBLOCK_CONSOLE))
59 printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");