src/soc/intel/tigerlake/graphics.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /*
  17  * This file is created based on Intel Tiger Lake Processor SA Datasheet
  18  * Document number: 571131
  19  * Chapter number: 4
  20  */
  21
  22 #include <arch/acpi.h>
  23 #include <console/console.h>
  24 #include <fsp/util.h>
  25 #include <device/device.h>
  26 #include <device/pci.h>
  27 #include <device/pci_ops.h>
  28 #include <drivers/intel/gma/i915_reg.h>
  29 #include <drivers/intel/gma/opregion.h>
  30 #include <intelblocks/graphics.h>
  31 #include <types.h>
  32
  33 uintptr_t fsp_soc_get_igd_bar(void)
  34 {
  35         return graphics_get_memory_base();
  36 }
  37
  38 void graphics_soc_init(struct device *dev)
  39 {
  40         uint32_t ddi_buf_ctl;
  41
  42         /* Skip IGD GT programming */
  43         if (CONFIG(SKIP_GRAPHICS_ENABLING))
  44                 return;
  45
  46         /*
  47          * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
  48          * This will allow the kernel to use 4-lane eDP links properly
  49          * if the VBIOS or GOP driver do not execute.
  50          */
  51         ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
  52         if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
  53                 ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED |
  54                                 DDI_BUF_IS_IDLE);
  55                 graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
  56         }
  57
  58         /*
  59          * GFX PEIM module inside FSP binary is taking care of graphics
  60          * initialization based on RUN_FSP_GOP Kconfig
  61          * option and input VBT file. Hence no need to load/execute legacy VGA
  62          * OpROM in order to initialize GFX.
  63          *
  64          * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
  65          * Kconfig to perform GFX initialization through VGA OpRom.
  66          */
  67         if (CONFIG(RUN_FSP_GOP))
  68                 return;
  69
  70         /* IGD needs to Bus Master */
  71         uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
  72         reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
  73         pci_write_config32(dev, PCI_COMMAND, reg32);
  74
  75         /* Initialize PCI device, load/execute BIOS Option ROM */
  76         pci_dev_init(dev);
  77 }
  78
  79 uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
  80                 uintptr_t current, struct acpi_rsdp *rsdp)
  81 {
  82         igd_opregion_t *opregion;
  83
  84         printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
  85         opregion = (igd_opregion_t *)current;
  86
  87         if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
  88                 return current;
  89
  90         current += sizeof(igd_opregion_t);
  91
  92         return acpi_align_current(current);
  93 }