src/soc/intel/skylake/pmutil.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 /*
  16  * Helper functions for dealing with power management registers
  17  * and the differences between PCH variants.
  18  */
  19
  20 #include <arch/acpi.h>
  21 #include <device/mmio.h>
  22 #include <device/pci_ops.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_def.h>
  26 #include <console/console.h>
  27 #include <intelblocks/pmclib.h>
  28 #include <intelblocks/lpc_lib.h>
  29 #include <intelblocks/tco.h>
  30 #include <soc/gpe.h>
  31 #include <soc/gpio.h>
  32 #include <soc/iomap.h>
  33 #include <soc/pci_devs.h>
  34 #include <soc/pm.h>
  35 #include <soc/pmc.h>
  36 #include <soc/smbus.h>
  37 #include <security/vboot/vbnv.h>
  38
  39 #include "chip.h"
  40
  41 /*
  42  * SMI
  43  */
  44
  45 const char *const *soc_smi_sts_array(size_t *smi_arr)
  46 {
  47         static const char *const smi_sts_bits[] = {
  48                 [2] = "BIOS",
  49                 [3] = "LEGACY_USB",
  50                 [4] = "SLP_SMI",
  51                 [5] = "APM",
  52                 [6] = "SWSMI_TMR",
  53                 [8] = "PM1",
  54                 [9] = "GPE0",
  55                 [10] = "GPI",
  56                 [11] = "MCSMI",
  57                 [12] = "DEVMON",
  58                 [13] = "TCO",
  59                 [14] = "PERIODIC",
  60                 [15] = "SERIRQ_SMI",
  61                 [16] = "SMBUS_SMI",
  62                 [17] = "LEGACY_USB2",
  63                 [18] = "INTEL_USB2",
  64                 [20] = "PCI_EXP_SMI",
  65                 [21] = "MONITOR",
  66                 [26] = "SPI",
  67                 [27] = "GPIO_UNLOCK",
  68                 [28] = "ESPI_SMI",
  69         };
  70
  71         *smi_arr = ARRAY_SIZE(smi_sts_bits);
  72         return smi_sts_bits;
  73 }
  74
  75 /*
  76  * TCO
  77  */
  78
  79 const char *const *soc_tco_sts_array(size_t *tco_arr)
  80 {
  81         static const char *const tco_sts_bits[] = {
  82                 [0] = "NMI2SMI",
  83                 [1] = "SW_TCO",
  84                 [2] = "TCO_INT",
  85                 [3] = "TIMEOUT",
  86                 [7] = "NEWCENTURY",
  87                 [8] = "BIOSWR",
  88                 [9] = "DMISCI",
  89                 [10] = "DMISMI",
  90                 [12] = "DMISERR",
  91                 [13] = "SLVSEL",
  92                 [16] = "INTRD_DET",
  93                 [17] = "SECOND_TO",
  94                 [18] = "BOOT",
  95                 [20] = "SMLINK_SLV"
  96         };
  97
  98         *tco_arr = ARRAY_SIZE(tco_sts_bits);
  99         return tco_sts_bits;
 100 }
 101
 102 /*
 103  * GPE0
 104  */
 105
 106 const char *const *soc_std_gpe_sts_array(size_t *gpe_arr)
 107 {
 108         static const char *const gpe_sts_bits[] = {
 109                 [1] = "HOTPLUG",
 110                 [2] = "SWGPE",
 111                 [6] = "TCO_SCI",
 112                 [7] = "SMB_WAK",
 113                 [9] = "PCI_EXP",
 114                 [10] = "BATLOW",
 115                 [11] = "PME",
 116                 [12] = "ME",
 117                 [13] = "PME_B0",
 118                 [14] = "eSPI",
 119                 [15] = "GPIO Tier-2",
 120                 [16] = "LAN_WAKE",
 121                 [18] = "WADT"
 122         };
 123
 124         *gpe_arr = ARRAY_SIZE(gpe_sts_bits);
 125         return gpe_sts_bits;
 126 }
 127
 128 int acpi_sci_irq(void)
 129 {
 130         int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
 131         int sci_irq = 9;
 132
 133         /* Determine how SCI is routed. */
 134         switch (scis) {
 135         case SCIS_IRQ9:
 136         case SCIS_IRQ10:
 137         case SCIS_IRQ11:
 138                 sci_irq = scis - SCIS_IRQ9 + 9;
 139                 break;
 140         case SCIS_IRQ20:
 141         case SCIS_IRQ21:
 142         case SCIS_IRQ22:
 143         case SCIS_IRQ23:
 144                 sci_irq = scis - SCIS_IRQ20 + 20;
 145                 break;
 146         default:
 147                 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
 148                 sci_irq = 9;
 149                 break;
 150         }
 151
 152         printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
 153         return sci_irq;
 154 }
 155
 156 uint8_t *pmc_mmio_regs(void)
 157 {
 158         uint32_t reg32;
 159
 160         reg32 = pci_read_config32(PCH_DEV_PMC, PWRMBASE);
 161
 162         /* 4KiB alignment. */
 163         reg32 &= ~0xfff;
 164
 165         return (void *)(uintptr_t) reg32;
 166 }
 167
 168 uintptr_t soc_read_pmc_base(void)
 169 {
 170         return (uintptr_t) (pmc_mmio_regs());
 171 }
 172
 173 uint32_t *soc_pmc_etr_addr(void)
 174 {
 175         /*
 176          * The pointer returned must not be cached, because the address depends on the
 177          * MMCONF base address and the assigned PCI bus number, which both may change
 178          * during the boot process!
 179          */
 180         return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR);
 181 }
 182
 183 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 184 {
 185         DEVTREE_CONST struct soc_intel_skylake_config *config;
 186
 187         config = config_of_soc();
 188
 189         /* Assign to out variable */
 190         *dw0 = config->gpe0_dw0;
 191         *dw1 = config->gpe0_dw1;
 192         *dw2 = config->gpe0_dw2;
 193 }
 194
 195 int rtc_failure(void)
 196 {
 197         u8 reg8;
 198         int rtc_failed;
 199         /* PMC Controller Device 0x1F, Func 02 */
 200 #if defined(__SIMPLE_DEVICE__)
 201         pci_devfn_t dev = PCH_DEV_PMC;
 202 #else
 203         struct device *dev = PCH_DEV_PMC;
 204 #endif
 205         reg8 = pci_read_config8(dev, GEN_PMCON_B);
 206         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 207         if (rtc_failed) {
 208                 reg8 &= ~RTC_BATTERY_DEAD;
 209                 pci_write_config8(dev, GEN_PMCON_B, reg8);
 210                 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 211         }
 212
 213         return !!rtc_failed;
 214 }
 215
 216 int vbnv_cmos_failed(void)
 217 {
 218         return rtc_failure();
 219 }
 220
 221 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 222 int soc_prev_sleep_state(const struct chipset_power_state *ps,
 223                                                 int prev_sleep_state)
 224 {
 225         /*
 226          * Check for any power failure to determine if this a wake from
 227          * S5 because the PCH does not set the WAK_STS bit when waking
 228          * from a true G3 state.
 229          */
 230         if (!(ps->pm1_sts & WAK_STS) &&
 231             (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
 232                 prev_sleep_state = ACPI_S5;
 233
 234         /*
 235          * If waking from S3 determine if deep S3 is enabled. If not,
 236          * need to check both deep sleep well and normal suspend well.
 237          * Otherwise just check deep sleep well.
 238          */
 239         if (prev_sleep_state == ACPI_S3) {
 240                 /* PWR_FLR represents deep sleep power well loss. */
 241                 uint32_t mask = PWR_FLR;
 242
 243                 /* If deep s3 isn't enabled check the suspend well too. */
 244                 if (!deep_s3_enabled())
 245                         mask |= SUS_PWR_FLR;
 246
 247                 if (ps->gen_pmcon_b & mask)
 248                         prev_sleep_state = ACPI_S5;
 249         }
 250         return prev_sleep_state;
 251 }
 252
 253 void soc_fill_power_state(struct chipset_power_state *ps)
 254 {
 255         uint8_t *pmc;
 256
 257         ps->tco1_sts = tco_read_reg(TCO1_STS);
 258         ps->tco2_sts = tco_read_reg(TCO2_STS);
 259
 260         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n",
 261                ps->tco1_sts, ps->tco2_sts);
 262
 263         ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
 264         ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
 265
 266         pmc = pmc_mmio_regs();
 267         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 268         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 269
 270         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 271                ps->gen_pmcon_a, ps->gen_pmcon_b);
 272
 273         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 274                ps->gblrst_cause[0], ps->gblrst_cause[1]);
 275 }
 276
 277 /* STM Support */
 278 uint16_t get_pmbase(void)
 279 {
 280         return ACPI_BASE_ADDRESS;
 281 }