src/soc/intel/skylake/cpu.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/cpu.h>
  16 #include <bootstate.h>
  17 #include <console/console.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <cpu/x86/mtrr.h>
  21 #include <cpu/x86/msr.h>
  22 #include <cpu/x86/lapic.h>
  23 #include <cpu/x86/mp.h>
  24 #include <cpu/intel/common/common.h>
  25 #include <cpu/intel/microcode.h>
  26 #include <cpu/intel/speedstep.h>
  27 #include <cpu/intel/turbo.h>
  28 #include <cpu/x86/cache.h>
  29 #include <cpu/x86/name.h>
  30 #include <cpu/x86/smm.h>
  31 #include <cpu/intel/smm_reloc.h>
  32 #include <intelblocks/cpulib.h>
  33 #include <intelblocks/fast_spi.h>
  34 #include <intelblocks/mp_init.h>
  35 #include <intelblocks/sgx.h>
  36 #include <soc/cpu.h>
  37 #include <soc/msr.h>
  38 #include <soc/pci_devs.h>
  39 #include <soc/pm.h>
  40 #include <soc/ramstage.h>
  41 #include <soc/systemagent.h>
  42 #include <timer.h>
  43
  44 #include "chip.h"
  45
  46 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
  47 static const u8 power_limit_time_sec_to_msr[] = {
  48         [0]   = 0x00,
  49         [1]   = 0x0a,
  50         [2]   = 0x0b,
  51         [3]   = 0x4b,
  52         [4]   = 0x0c,
  53         [5]   = 0x2c,
  54         [6]   = 0x4c,
  55         [7]   = 0x6c,
  56         [8]   = 0x0d,
  57         [10]  = 0x2d,
  58         [12]  = 0x4d,
  59         [14]  = 0x6d,
  60         [16]  = 0x0e,
  61         [20]  = 0x2e,
  62         [24]  = 0x4e,
  63         [28]  = 0x6e,
  64         [32]  = 0x0f,
  65         [40]  = 0x2f,
  66         [48]  = 0x4f,
  67         [56]  = 0x6f,
  68         [64]  = 0x10,
  69         [80]  = 0x30,
  70         [96]  = 0x50,
  71         [112] = 0x70,
  72         [128] = 0x11,
  73 };
  74
  75 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
  76 static const u8 power_limit_time_msr_to_sec[] = {
  77         [0x00] = 0,
  78         [0x0a] = 1,
  79         [0x0b] = 2,
  80         [0x4b] = 3,
  81         [0x0c] = 4,
  82         [0x2c] = 5,
  83         [0x4c] = 6,
  84         [0x6c] = 7,
  85         [0x0d] = 8,
  86         [0x2d] = 10,
  87         [0x4d] = 12,
  88         [0x6d] = 14,
  89         [0x0e] = 16,
  90         [0x2e] = 20,
  91         [0x4e] = 24,
  92         [0x6e] = 28,
  93         [0x0f] = 32,
  94         [0x2f] = 40,
  95         [0x4f] = 48,
  96         [0x6f] = 56,
  97         [0x10] = 64,
  98         [0x30] = 80,
  99         [0x50] = 96,
 100         [0x70] = 112,
 101         [0x11] = 128,
 102 };
 103
 104 /*
 105  * Configure processor power limits if possible
 106  * This must be done AFTER set of BIOS_RESET_CPL
 107  */
 108 void set_power_limits(u8 power_limit_1_time)
 109 {
 110         msr_t msr = rdmsr(MSR_PLATFORM_INFO);
 111         msr_t limit;
 112         unsigned int power_unit;
 113         unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
 114         u8 power_limit_1_val;
 115
 116         config_t *conf = config_of_soc();
 117
 118         if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
 119                 power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
 120
 121         if (!(msr.lo & PLATFORM_INFO_SET_TDP))
 122                 return;
 123
 124         /* Get units */
 125         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 126         power_unit = 1 << (msr.lo & 0xf);
 127
 128         /* Get power defaults for this SKU */
 129         msr = rdmsr(MSR_PKG_POWER_SKU);
 130         tdp = msr.lo & 0x7fff;
 131         min_power = (msr.lo >> 16) & 0x7fff;
 132         max_power = msr.hi & 0x7fff;
 133         max_time = (msr.hi >> 16) & 0x7f;
 134
 135         printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
 136
 137         if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
 138                 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
 139
 140         if (min_power > 0 && tdp < min_power)
 141                 tdp = min_power;
 142
 143         if (max_power > 0 && tdp > max_power)
 144                 tdp = max_power;
 145
 146         power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
 147
 148         /* Set long term power limit to TDP */
 149         limit.lo = 0;
 150         tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
 151                 tdp : (conf->tdp_pl1_override * power_unit));
 152         limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
 153
 154         /* Set PL1 Pkg Power clamp bit */
 155         limit.lo |= PKG_POWER_LIMIT_CLAMP;
 156
 157         limit.lo |= PKG_POWER_LIMIT_EN;
 158         limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
 159                 PKG_POWER_LIMIT_TIME_SHIFT;
 160
 161         /* Set short term power limit to 1.25 * TDP if no config given */
 162         limit.hi = 0;
 163         tdp_pl2 = (conf->tdp_pl2_override == 0) ?
 164                 (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);
 165         printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit);
 166         limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;
 167         limit.hi |= PKG_POWER_LIMIT_CLAMP;
 168         limit.hi |= PKG_POWER_LIMIT_EN;
 169
 170         /* Power limit 2 time is only programmable on server SKU */
 171         wrmsr(MSR_PKG_POWER_LIMIT, limit);
 172
 173         /* Set PL2 power limit values in MCHBAR and disable PL1 */
 174         MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));
 175         MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
 176
 177         /* Set PsysPl2 */
 178         if (conf->tdp_psyspl2) {
 179                 limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
 180                 limit.hi = 0;
 181                 printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n",
 182                         conf->tdp_psyspl2);
 183                 limit.hi |= (conf->tdp_psyspl2 * power_unit) &
 184                         PKG_POWER_LIMIT_MASK;
 185                 limit.hi |= PKG_POWER_LIMIT_CLAMP;
 186                 limit.hi |= PKG_POWER_LIMIT_EN;
 187
 188                 wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
 189         }
 190
 191         /* Set PsysPl3 */
 192         if (conf->tdp_psyspl3) {
 193                 limit = rdmsr(MSR_PL3_CONTROL);
 194                 limit.lo = 0;
 195                 printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
 196                        conf->tdp_psyspl3);
 197                 limit.lo |= (conf->tdp_psyspl3 * power_unit) &
 198                         PKG_POWER_LIMIT_MASK;
 199                 /* Enable PsysPl3 */
 200                 limit.lo |= PKG_POWER_LIMIT_EN;
 201                 /* set PsysPl3 time window */
 202                 limit.lo |= (conf->tdp_psyspl3_time &
 203                              PKG_POWER_LIMIT_TIME_MASK) <<
 204                         PKG_POWER_LIMIT_TIME_SHIFT;
 205                 /* set PsysPl3  duty cycle */
 206                 limit.lo |= (conf->tdp_psyspl3_dutycycle &
 207                              PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
 208                         PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
 209                 wrmsr(MSR_PL3_CONTROL, limit);
 210         }
 211
 212         /* Set Pl4 */
 213         if (conf->tdp_pl4) {
 214                 limit = rdmsr(MSR_VR_CURRENT_CONFIG);
 215                 limit.lo = 0;
 216                 printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n",
 217                        conf->tdp_pl4);
 218                 limit.lo |= (conf->tdp_pl4 * power_unit) &
 219                         PKG_POWER_LIMIT_MASK;
 220                 wrmsr(MSR_VR_CURRENT_CONFIG, limit);
 221         }
 222
 223         /* Set DDR RAPL power limit by copying from MMIO to MSR */
 224         msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
 225         msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
 226         wrmsr(MSR_DDR_RAPL_LIMIT, msr);
 227
 228         /* Use nominal TDP values for CPUs with configurable TDP */
 229         if (cpu_config_tdp_levels()) {
 230                 limit.hi = 0;
 231                 limit.lo = cpu_get_tdp_nominal_ratio();
 232                 wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
 233         }
 234 }
 235
 236 static void configure_thermal_target(void)
 237 {
 238         config_t *conf = config_of_soc();
 239         msr_t msr;
 240
 241
 242         /* Set TCC activation offset if supported */
 243         msr = rdmsr(MSR_PLATFORM_INFO);
 244         if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
 245                 msr = rdmsr(MSR_TEMPERATURE_TARGET);
 246                 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
 247                 msr.lo |= (conf->tcc_offset & 0xf) << 24;
 248                 wrmsr(MSR_TEMPERATURE_TARGET, msr);
 249         }
 250         msr = rdmsr(MSR_TEMPERATURE_TARGET);
 251         msr.lo &= ~0x7f; /* Bits 6:0 */
 252         msr.lo |= 0xe6; /* setting 100ms thermal time window */
 253         wrmsr(MSR_TEMPERATURE_TARGET, msr);
 254 }
 255
 256 static void configure_isst(void)
 257 {
 258         config_t *conf = config_of_soc();
 259         msr_t msr;
 260
 261
 262         if (conf->speed_shift_enable) {
 263                 /*
 264                 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
 265                   is supported or not. coreboot needs to configure MSR 0x1AA
 266                   which is then reflected in the CPUID register.
 267                 */
 268                 msr = rdmsr(MSR_MISC_PWR_MGMT);
 269                 msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
 270                 msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
 271                 msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
 272                 wrmsr(MSR_MISC_PWR_MGMT, msr);
 273         } else {
 274                 msr = rdmsr(MSR_MISC_PWR_MGMT);
 275                 msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
 276                 msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
 277                 msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
 278                 wrmsr(MSR_MISC_PWR_MGMT, msr);
 279         }
 280 }
 281
 282 static void configure_misc(void)
 283 {
 284         config_t *conf = config_of_soc();
 285         msr_t msr;
 286
 287
 288         msr = rdmsr(IA32_MISC_ENABLE);
 289         msr.lo |= (1 << 0);     /* Fast String enable */
 290         msr.lo |= (1 << 3);     /* TM1/TM2/EMTTM enable */
 291         wrmsr(IA32_MISC_ENABLE, msr);
 292
 293         /* Set EIST status */
 294         cpu_set_eist(conf->eist_enable);
 295
 296         /* Disable Thermal interrupts */
 297         msr.lo = 0;
 298         msr.hi = 0;
 299         wrmsr(IA32_THERM_INTERRUPT, msr);
 300
 301         /* Enable package critical interrupt only */
 302         msr.lo = 1 << 4;
 303         msr.hi = 0;
 304         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
 305
 306         msr = rdmsr(MSR_POWER_CTL);
 307         msr.lo |= (1 << 0);     /* Enable Bi-directional PROCHOT as an input*/
 308         msr.lo |= (1 << 18);    /* Enable Energy/Performance Bias control */
 309         msr.lo &= ~POWER_CTL_C1E_MASK;  /* Disable C1E */
 310         msr.lo |= (1 << 23);    /* Lock it */
 311         wrmsr(MSR_POWER_CTL, msr);
 312 }
 313
 314 static void enable_lapic_tpr(void)
 315 {
 316         msr_t msr;
 317
 318         msr = rdmsr(MSR_PIC_MSG_CONTROL);
 319         msr.lo &= ~(1 << 10);   /* Enable APIC TPR updates */
 320         wrmsr(MSR_PIC_MSG_CONTROL, msr);
 321 }
 322
 323 static void configure_dca_cap(void)
 324 {
 325         uint32_t feature_flag;
 326         msr_t msr;
 327
 328         /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
 329         feature_flag = cpu_get_feature_flags_ecx();
 330         if (feature_flag & CPUID_DCA) {
 331                 msr = rdmsr(IA32_PLATFORM_DCA_CAP);
 332                 msr.lo |= 1;
 333                 wrmsr(IA32_PLATFORM_DCA_CAP, msr);
 334         }
 335 }
 336
 337 static void set_energy_perf_bias(u8 policy)
 338 {
 339         msr_t msr;
 340         int ecx;
 341
 342         /* Determine if energy efficient policy is supported. */
 343         ecx = cpuid_ecx(0x6);
 344         if (!(ecx & (1 << 3)))
 345                 return;
 346
 347         /* Energy Policy is bits 3:0 */
 348         msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 349         msr.lo &= ~0xf;
 350         msr.lo |= policy & 0xf;
 351         wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 352
 353         printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);
 354 }
 355
 356 static void configure_c_states(void)
 357 {
 358         msr_t msr;
 359
 360         /* C-state Interrupt Response Latency Control 0 - package C3 latency */
 361         msr.hi = 0;
 362         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
 363         wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);
 364
 365         /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
 366         msr.hi = 0;
 367         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
 368         wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
 369
 370         /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
 371         msr.hi = 0;
 372         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 373         wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 374
 375         /* C-state Interrupt Response Latency Control 3 - package C8 */
 376         msr.hi = 0;
 377         msr.lo = IRTL_VALID | IRTL_1024_NS |
 378                 C_STATE_LATENCY_CONTROL_3_LIMIT;
 379         wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 380
 381         /* C-state Interrupt Response Latency Control 4 - package C9 */
 382         msr.hi = 0;
 383         msr.lo = IRTL_VALID | IRTL_1024_NS |
 384                 C_STATE_LATENCY_CONTROL_4_LIMIT;
 385         wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 386
 387         /* C-state Interrupt Response Latency Control 5 - package C10 */
 388         msr.hi = 0;
 389         msr.lo = IRTL_VALID | IRTL_1024_NS |
 390                 C_STATE_LATENCY_CONTROL_5_LIMIT;
 391         wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 392 }
 393
 394 /*
 395  * The emulated ACPI timer allows disabling of the ACPI timer
 396  * (PM1_TMR) to have no impart on the system.
 397  */
 398 static void enable_pm_timer_emulation(void)
 399 {
 400         /* ACPI PM timer emulation */
 401         msr_t msr;
 402         /*
 403          * The derived frequency is calculated as follows:
 404          *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
 405          * Back solve the multiplier so the 3.579545MHz ACPI timer
 406          * frequency is used.
 407          */
 408         msr.hi = (3579545ULL << 32) / CTC_FREQ;
 409         /* Set PM1 timer IO port and enable */
 410         msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 411                         EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
 412         wrmsr(MSR_EMULATE_PM_TIMER, msr);
 413 }
 414
 415 /*
 416  * Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling
 417  * as suggested in Intel document 325384-070US.
 418  */
 419 static void cpu_lock_aesni(void)
 420 {
 421         msr_t msr;
 422
 423         /* Only run once per core as specified in the MSR datasheet */
 424         if (intel_ht_sibling())
 425                 return;
 426
 427         msr = rdmsr(MSR_FEATURE_CONFIG);
 428         if ((msr.lo & 1) == 0) {
 429                 msr.lo |= 1;
 430                 wrmsr(MSR_FEATURE_CONFIG, msr);
 431         }
 432 }
 433
 434 /* All CPUs including BSP will run the following function. */
 435 void soc_core_init(struct device *cpu)
 436 {
 437         /* Clear out pending MCEs */
 438         /* TODO(adurbin): This should only be done on a cold boot. Also, some
 439          * of these banks are core vs package scope. For now every CPU clears
 440          * every bank. */
 441         mca_configure();
 442
 443         /* Enable the local CPU apics */
 444         enable_lapic_tpr();
 445         setup_lapic();
 446
 447         /* Configure c-state interrupt response time */
 448         configure_c_states();
 449
 450         /* Configure Enhanced SpeedStep and Thermal Sensors */
 451         configure_misc();
 452
 453         /* Configure Intel Speed Shift */
 454         configure_isst();
 455
 456         /* Lock AES-NI MSR */
 457         cpu_lock_aesni();
 458
 459         /* Enable ACPI Timer Emulation via MSR 0x121 */
 460         enable_pm_timer_emulation();
 461
 462         /* Enable Direct Cache Access */
 463         configure_dca_cap();
 464
 465         /* Set energy policy */
 466         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 467
 468         /* Enable Turbo */
 469         enable_turbo();
 470
 471         /* Configure Core PRMRR for SGX. */
 472         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
 473                 prmrr_core_configure();
 474 }
 475
 476 static void per_cpu_smm_trigger(void)
 477 {
 478         /* Relocate the SMM handler. */
 479         smm_relocate();
 480 }
 481
 482 static void vmx_configure(void *unused)
 483 {
 484         set_feature_ctrl_vmx();
 485 }
 486
 487 static void fc_lock_configure(void *unused)
 488 {
 489         set_feature_ctrl_lock();
 490 }
 491
 492 static void post_mp_init(void)
 493 {
 494         int ret = 0;
 495
 496         /* Set Max Ratio */
 497         cpu_set_max_ratio();
 498
 499         /*
 500          * Now that all APs have been relocated as well as the BSP let SMIs
 501          * start flowing.
 502          */
 503         smm_southbridge_enable(GBL_EN);
 504
 505         /* Lock down the SMRAM space. */
 506         if (CONFIG(HAVE_SMI_HANDLER))
 507                 smm_lock();
 508
 509         ret |= mp_run_on_all_cpus(vmx_configure, NULL);
 510
 511         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
 512                 ret |= mp_run_on_all_cpus(sgx_configure, NULL);
 513
 514         ret |= mp_run_on_all_cpus(fc_lock_configure, NULL);
 515
 516         if (ret)
 517                 printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n");
 518 }
 519
 520 static const struct mp_ops mp_ops = {
 521         /*
 522          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 523          * that are set prior to ramstage.
 524          * Real MTRRs programming are being done after resource allocation.
 525          */
 526         .pre_mp_init = soc_fsp_load,
 527         .get_cpu_count = get_cpu_count,
 528         .get_smm_info = smm_info,
 529         .get_microcode_info = get_microcode_info,
 530         .pre_mp_smm_init = smm_initialize,
 531         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 532         .relocation_handler = smm_relocation_handler,
 533         .post_mp_init = post_mp_init,
 534 };
 535
 536 void soc_init_cpus(struct bus *cpu_bus)
 537 {
 538         if (mp_init_with_smm(cpu_bus, &mp_ops))
 539                 printk(BIOS_ERR, "MP initialization failure.\n");
 540
 541         /* Thermal throttle activation offset */
 542         configure_thermal_target();
 543 }
 544
 545 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 546 {
 547         msr_t msr1;
 548         msr_t msr2;
 549
 550         /*
 551          * If PRMRR/SGX is supported the FIT microcode load will set the msr
 552          * 0x08b with the Patch revision id one less than the id in the
 553          * microcode binary. The PRMRR support is indicated in the MSR
 554          * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the
 555          * same microcode during CPU initialization. If SGX is enabled, as
 556          * part of SGX BIOS initialization steps, the same microcode needs to
 557          * be reloaded after the core PRMRR MSRs are programmed.
 558          */
 559         msr1 = rdmsr(MTRR_CAP_MSR);
 560         msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);
 561         if (msr2.lo && (current_patch_id == new_patch_id - 1))
 562                 return 0;
 563         else
 564                 return (msr1.lo & PRMRR_SUPPORTED) &&
 565                         (current_patch_id == new_patch_id - 1);
 566 }