src/soc/intel/skylake/bootblock/pch.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <device/pci_ops.h>
  15 #include <device/device.h>
  16 #include <device/pci_def.h>
  17 #include <intelblocks/cse.h>
  18 #include <intelblocks/fast_spi.h>
  19 #include <intelblocks/itss.h>
  20 #include <intelblocks/lpc_lib.h>
  21 #include <intelblocks/p2sb.h>
  22 #include <intelblocks/pcr.h>
  23 #include <intelblocks/pmclib.h>
  24 #include <intelblocks/rtc.h>
  25 #include <soc/bootblock.h>
  26 #include <soc/iomap.h>
  27 #include <soc/p2sb.h>
  28 #include <soc/pch.h>
  29 #include <soc/pci_devs.h>
  30 #include <soc/pcr_ids.h>
  31 #include <soc/pm.h>
  32 #include <soc/pmc.h>
  33 #include "../chip.h"
  34
  35 #define PCR_DMI_DMICTL          0x2234
  36 #define  PCR_DMI_DMICTL_SRLOCK  (1 << 31)
  37 #define PCR_DMI_ACPIBA          0x27B4
  38 #define PCR_DMI_ACPIBDID        0x27B8
  39 #define PCR_DMI_PMBASEA         0x27AC
  40 #define PCR_DMI_PMBASEC         0x27B0
  41
  42 void bootblock_pch_early_init(void)
  43 {
  44         fast_spi_early_init(SPI_BASE_ADDRESS);
  45         p2sb_enable_bar();
  46         p2sb_configure_hpet();
  47 }
  48
  49 static void soc_config_acpibase(void)
  50 {
  51         uint32_t reg32;
  52
  53         /* Disable ABASE in PMC Device first before changing Base Address */
  54         reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
  55         pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN);
  56
  57         /* Program ACPI Base */
  58         pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
  59
  60         /* Enable ACPI in PMC */
  61         pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN);
  62
  63         /*
  64          * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0]
  65          * to [0x3F, PMC PCI Offset 40h bit[15:2], 1]
  66          */
  67         reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);
  68         pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
  69         if (CONFIG(SKYLAKE_SOC_PCH_H))
  70                 pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
  71         else
  72                 pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0);
  73 }
  74
  75 static void soc_config_pwrmbase(void)
  76 {
  77         uint32_t reg32;
  78
  79         /* Disable PWRMBASE in PMC Device first before changing Base address */
  80         reg32 = pci_read_config32(PCH_DEV_PMC, ACTL);
  81         pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN);
  82
  83         /* Program PWRM Base */
  84         pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
  85
  86         /* Enable PWRM in PMC */
  87         pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN);
  88
  89         /*
  90          * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0]
  91          * to the same value programmed in PMC PCI Offset 48h bit[31:16],
  92          * this has an implication of making sure the PWRMBASE to be
  93          * 64KB aligned.
  94          *
  95          * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
  96          * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
  97          * implication of making sure the memory allocated to PWRMBASE to be
  98          * 64KB in size.
  99          */
 100         pcr_write32(PID_DMI, PCR_DMI_PMBASEA,
 101                 ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
 102                  (PCH_PWRM_BASE_ADDRESS >> 16)));
 103         if (CONFIG(SKYLAKE_SOC_PCH_H))
 104                 pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);
 105         else
 106                 pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
 107 }
 108
 109 static int pch_check_decode_enable(void)
 110 {
 111         uint32_t dmi_control;
 112
 113         /*
 114          * This cycle decoding is only allowed to set when
 115          * DMICTL.SRLOCK is 0.
 116          */
 117         dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
 118         if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
 119                 return -1;
 120         return 0;
 121 }
 122
 123 void pch_early_iorange_init(void)
 124 {
 125         uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
 126                         LPC_IOE_EC_62_66;
 127
 128         const config_t *config = config_of_soc();
 129
 130         if (config->lpc_ioe) {
 131                 io_enables = config->lpc_ioe & 0x3f0f;
 132                 lpc_set_fixed_io_ranges(config->lpc_iod, 0x1377);
 133         } else {
 134                 /* IO Decode Range */
 135                 if (CONFIG(DRIVERS_UART_8250IO))
 136                         lpc_io_setup_comm_a_b();
 137         }
 138
 139         /* IO Decode Enable */
 140         if (pch_check_decode_enable() == 0) {
 141                 io_enables = lpc_enable_fixed_io_ranges(io_enables);
 142                 /*
 143                  * As per PCH BWG 2.5.1.6.
 144                  * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
 145                  * value programmed in LPC PCI offset 82h.
 146                  */
 147                 pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
 148                 /*
 149                  * As per PCH BWG 2.5.1.5.
 150                  * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
 151                  * value programmed in LPC PCI offset 80h.
 152                  */
 153                 pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
 154         }
 155
 156         /* Program generic IO Decode Range */
 157         pch_enable_lpc();
 158 }
 159
 160 void bootblock_pch_init(void)
 161 {
 162         /*
 163          * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
 164          * GPE0_STS, GPE0_EN registers.
 165          */
 166         soc_config_acpibase();
 167
 168         /*
 169          * Enabling PWRM Base for accessing
 170          * Global Reset Cause Register.
 171          */
 172         soc_config_pwrmbase();
 173
 174         /* Set up GPE configuration */
 175         pmc_gpe_init();
 176
 177         enable_rtc_upper_bank();
 178
 179         /* initialize Heci interface */
 180         heci_init(HECI1_BASE_ADDRESS);
 181 }