src/soc/intel/skylake/acpi/systemagent.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <soc/iomap.h>
  16
  17 Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
  18 Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
  19 Name (_SEG, Zero)  // _SEG: PCI Segment
  20 Name (_UID, Zero)  // _UID: Unique ID
  21
  22 Device (MCHC)
  23 {
  24         Name (_ADR, 0x00000000)
  25
  26         OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
  27         Field (MCHP, DWordAcc, NoLock, Preserve)
  28         {
  29                 Offset(0x40),   /* EPBAR (0:0:0:40) */
  30                 EPEN, 1,        /* Enable */
  31                 , 11,
  32                 EPBR, 27,       /* EPBAR [38:12] */
  33
  34                 Offset(0x48),   /* MCHBAR (0:0:0:48) */
  35                 MHEN, 1,        /* Enable */
  36                 , 14,
  37                 MHBR, 24,       /* MCHBAR [38:15] */
  38
  39                 Offset(0x60),   /* PCIEXBAR (0:0:0:60) */
  40                 PXEN, 1,        /* Enable */
  41                 PXSZ, 2,        /* PCI Express Size */
  42                 , 23,
  43                 PXBR, 13,       /* PCI Express BAR [38:26] */
  44
  45                 Offset(0x68),   /* DMIBAR (0:0:0:68) */
  46                 DIEN, 1,        /* Enable */
  47                 , 11,
  48                 DIBR, 27,       /* DMIBAR [38:12] */
  49
  50                 Offset (0x70),  /* ME Base Address */
  51                 MEBA, 64,
  52
  53                 Offset (0xa0),
  54                 TOM, 64,        /* Top of Used Memory */
  55                 TUUD, 64,       /* Top of Upper Used Memory */
  56
  57                 Offset (0xbc),  /* Top of Low Used Memory */
  58                 TLUD, 32,
  59         }
  60 }
  61
  62 Method (_CRS, 0, Serialized)
  63 {
  64         Name (MCRS, ResourceTemplate ()
  65         {
  66                 /* Bus Numbers */
  67                 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
  68                                 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
  69
  70                 /* IO Region 0 */
  71                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
  72                                 EntireRange,
  73                                 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
  74
  75                 /* PCI Config Space */
  76                 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
  77
  78                 /* IO Region 1 */
  79                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
  80                                 EntireRange,
  81                                 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
  82
  83                 /* VGA memory (0xa0000-0xbffff) */
  84                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  85                                 Cacheable, ReadWrite,
  86                                 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
  87                                 0x00020000)
  88
  89                 /*  OPROM reserved (0xc0000-0xc3fff) */
  90                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  91                                 Cacheable, ReadWrite,
  92                                 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
  93                                 0x00004000)
  94
  95                 /* OPROM reserved (0xc4000-0xc7fff) */
  96                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
  97                                 Cacheable, ReadWrite,
  98                                 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
  99                                 0x00004000)
 100
 101                 /* OPROM reserved (0xc8000-0xcbfff) */
 102                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 103                                 Cacheable, ReadWrite,
 104                                 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
 105                                 0x00004000)
 106
 107                 /* OPROM reserved (0xcc000-0xcffff) */
 108                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 109                                 Cacheable, ReadWrite,
 110                                 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
 111                                 0x00004000)
 112
 113                 /* OPROM reserved (0xd0000-0xd3fff) */
 114                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 115                                 Cacheable, ReadWrite,
 116                                 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
 117                                 0x00004000)
 118
 119                 /* OPROM reserved (0xd4000-0xd7fff) */
 120                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 121                                 Cacheable, ReadWrite,
 122                                 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
 123                                 0x00004000)
 124
 125                 /* OPROM reserved (0xd8000-0xdbfff) */
 126                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 127                                 Cacheable, ReadWrite,
 128                                 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
 129                                 0x00004000)
 130
 131                 /* OPROM reserved (0xdc000-0xdffff) */
 132                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 133                                 Cacheable, ReadWrite,
 134                                 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 135                                 0x00004000)
 136
 137                 /* BIOS Extension (0xe0000-0xe3fff) */
 138                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 139                                 Cacheable, ReadWrite,
 140                                 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
 141                                 0x00004000)
 142
 143                 /* BIOS Extension (0xe4000-0xe7fff) */
 144                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 145                                 Cacheable, ReadWrite,
 146                                 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
 147                                 0x00004000)
 148
 149                 /* BIOS Extension (0xe8000-0xebfff) */
 150                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 151                                 Cacheable, ReadWrite,
 152                                 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
 153                                 0x00004000)
 154
 155                 /* BIOS Extension (0xec000-0xeffff) */
 156                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 157                                 Cacheable, ReadWrite,
 158                                 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
 159                                 0x00004000)
 160
 161                 /* System BIOS (0xf0000-0xfffff) */
 162                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 163                                 Cacheable, ReadWrite,
 164                                 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 165                                 0x00010000)
 166
 167                 /* PCI Memory Region (TLUD - 0xdfffffff) */
 168                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 169                                 NonCacheable, ReadWrite,
 170                                 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
 171                                 0xE0000000,,, PM01)
 172
 173                 /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
 174                 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 175                                 NonCacheable, ReadWrite,
 176                                 0x00000000, 0x10000, 0x1ffff, 0x00000000,
 177                                 0x10000,,, PM02)
 178
 179                 /* PCH reserved resource (0xfc800000-0xfe7fffff) */
 180                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 181                                 Cacheable, ReadWrite,
 182                                 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
 183                                 0x00000000, PCH_PRESERVED_BASE_SIZE)
 184
 185 #if !CONFIG(TPM_CR50)
 186                 /* TPM Area (0xfed40000-0xfed44fff) */
 187                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 188                                 Cacheable, ReadWrite,
 189                                 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
 190                                 0x00005000)
 191 #endif
 192 })
 193
 194         /* Find PCI resource area in MCRS */
 195         CreateDwordField (MCRS, PM01._MIN, PMIN)
 196         CreateDwordField (MCRS, PM01._MAX, PMAX)
 197         CreateDwordField (MCRS, PM01._LEN, PLEN)
 198
 199         /*
 200          * Fix up PCI memory region
 201          * Start with Top of Lower Usable DRAM
 202          */
 203         Store (\_SB.PCI0.MCHC.TLUD, Local0)
 204         Store (\_SB.PCI0.MCHC.MEBA, Local1)
 205
 206         /*  Check if ME base is equal */
 207         If (LEqual (Local0, Local1)) {
 208                 /*  Use Top Of Memory instead */
 209                 Store (\_SB.PCI0.MCHC.TOM, Local0)
 210         }
 211
 212         Store (Local0, PMIN)
 213         Add (Subtract (PMAX, PMIN), 1, PLEN)
 214
 215         /* Patch PM02 range based on Memory Size */
 216         If (LEqual (A4GS, 0)) {
 217                 CreateQwordField (MCRS, PM02._LEN, MSEN)
 218                 Store (0, MSEN)
 219         } Else {
 220                 CreateQwordField (MCRS, PM02._MIN, MMIN)
 221                 CreateQwordField (MCRS, PM02._MAX, MMAX)
 222                 CreateQwordField (MCRS, PM02._LEN, MLEN)
 223                 /* Set 64bit MMIO resource base and length */
 224                 Store (A4GS, MLEN)
 225                 Store (A4GB, MMIN)
 226                 Subtract (Add (MMIN, MLEN), 1, MMAX)
 227         }
 228
 229         Return (MCRS)
 230 }
 231
 232 /* Get MCH BAR */
 233 Method (GMHB, 0, Serialized)
 234 {
 235         ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0)
 236         Return (Local0)
 237 }
 238
 239 /* Get EP BAR */
 240 Method (GEPB, 0, Serialized)
 241 {
 242         ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0)
 243         Return (Local0)
 244 }
 245
 246 /* Get PCIe BAR */
 247 Method (GPCB, 0, Serialized)
 248 {
 249         ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0)
 250         Return (Local0)
 251 }
 252
 253 /* Get PCIe Length */
 254 Method (GPCL, 0, Serialized)
 255 {
 256         ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0)
 257         Return (Local0)
 258 }
 259
 260 /* Get DMI BAR */
 261 Method (GDMB, 0, Serialized)
 262 {
 263         ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0)
 264         Return (Local0)
 265 }
 266
 267 /* PCI Device Resource Consumption */
 268 Device (PDRC)
 269 {
 270         Name (_HID, EISAID ("PNP0C02"))
 271         Name (_UID, 1)
 272
 273         Method (_CRS, 0, Serialized)
 274         {
 275                 Name (BUF0, ResourceTemplate ()
 276                 {
 277                         /* MCH BAR _BAS will be updated in _CRS below according to
 278                          * B0:D0:F0:Reg.48h
 279                          */
 280                         Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
 281
 282                         /* DMI BAR _BAS will be updated in _CRS below according to
 283                          * B0:D0:F0:Reg.68h
 284                          */
 285                         Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
 286
 287                         /* EP BAR _BAS will be updated in _CRS below according to
 288                          * B0:D0:F0:Reg.40h
 289                          */
 290                         Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
 291
 292                         /* PCI Express BAR _BAS and _LEN will be updated in
 293                          * _CRS below according to B0:D0:F0:Reg.60h
 294                          */
 295                         Memory32Fixed (ReadWrite, 0, 0, PCIX)
 296
 297                         /* VTD engine memory range. */
 298                         Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
 299
 300                         /* FLASH range */
 301                         Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
 302
 303                         /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
 304                         Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
 305
 306                         /* HPET address decode range */
 307                         Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
 308                 })
 309
 310                 CreateDwordField (BUF0, MCHB._BAS, MBR0)
 311                 Store (\_SB.PCI0.GMHB (), MBR0)
 312
 313                 CreateDwordField (BUF0, DMIB._BAS, DBR0)
 314                 Store (\_SB.PCI0.GDMB (), DBR0)
 315
 316                 CreateDwordField (BUF0, EGPB._BAS, EBR0)
 317                 Store (\_SB.PCI0.GEPB (), EBR0)
 318
 319                 CreateDwordField (BUF0, PCIX._BAS, XBR0)
 320                 Store (\_SB.PCI0.GPCB (), XBR0)
 321
 322                 CreateDwordField (BUF0, PCIX._LEN, XSZ0)
 323                 Store (\_SB.PCI0.GPCL (), XSZ0)
 324
 325                 CreateDwordField (BUF0, FIOH._BAS, FBR0)
 326                 Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0)
 327
 328                 Return (BUF0)
 329         }
 330 }