| blob | 8c0b62a9b961b338f4c9165c4293675913948e5c |
1 /*
2 * This file is part of the coreboot project.
3 *
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
15 #include <soc/interrupt.h>
16 #include <soc/irq.h>
18 Name (PICP, Package () {
19 /* D31: cAVS, SMBus, GbE, Nothpeak */
20 Package () { 0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
21 Package () { 0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
22 Package () { 0x001FFFFF, 2, 0, GbE_INTC_IRQ },
23 Package () { 0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
24 /* D30: SerialIo and SCS */
25 Package () { 0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
26 Package () { 0x001EFFFF, 1, 0, eMMC_IRQ },
27 Package () { 0x001EFFFF, 2, 0, SDIO_IRQ },
28 Package () { 0x001EFFFF, 3, 0, SD_IRQ },
29 /* D29: PCI Express Port 9-16 */
30 Package () { 0x001DFFFF, 0, 0, PCIE_9_IRQ },
31 Package () { 0x001DFFFF, 1, 0, PCIE_10_IRQ },
32 Package () { 0x001DFFFF, 2, 0, PCIE_11_IRQ },
33 Package () { 0x001DFFFF, 3, 0, PCIE_12_IRQ },
34 /* D28: PCI Express Port 1-8 */
35 Package () { 0x001CFFFF, 0, 0, PCIE_1_IRQ },
36 Package () { 0x001CFFFF, 1, 0, PCIE_2_IRQ },
37 Package () { 0x001CFFFF, 2, 0, PCIE_3_IRQ },
38 Package () { 0x001CFFFF, 3, 0, PCIE_4_IRQ },
39 /* D25: SerialIo */
40 Package () { 0x0019FFFF, 0, 0, LPSS_UART2_IRQ },
41 Package () { 0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
42 Package () { 0x0019FFFF, 2, 0, LPSS_I2C4_IRQ },
43 /* D22: CSME (HECI, IDE-R, KT redirection */
44 Package () { 0x0016FFFF, 0, 0, HECI_1_IRQ },
45 Package () { 0x0016FFFF, 1, 0, HECI_2_IRQ },
46 Package () { 0x0016FFFF, 2, 0, IDER_IRQ },
47 Package () { 0x0016FFFF, 3, 0, KT_IRQ },
48 /* D23: Sata controller */
49 Package () { 0x0017FFFF, 0, 0, SATA_IRQ },
50 /* D21: SerialIo */
51 Package () { 0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
52 Package () { 0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
53 Package () { 0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
54 Package () { 0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
55 /* D20: xHCI, OTG, Thermal, Camera */
56 Package () { 0x0014FFFF, 0, 0, XHCI_IRQ },
57 Package () { 0x0014FFFF, 1, 0, OTG_IRQ },
58 Package () { 0x0014FFFF, 2, 0, THERMAL_IRQ },
59 Package () { 0x0014FFFF, 3, 0, CIO_INTD_IRQ },
60 /* D19: Integrated Sensor Hub */
61 Package () { 0x0013FFFF, 0, 0, ISH_IRQ },
62 /* P.E.G. Root Port D1F0 */
63 Package () { 0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
64 Package () { 0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
65 Package () { 0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
66 Package () { 0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
67 /* SA IGFX Device */
68 Package () { 0x0002FFFF, 0, 0, IGFX_IRQ },
69 /* SA Thermal Device */
70 Package () { 0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
71 /* SA SkyCam Device */
72 Package () { 0x0005FFFF, 0, 0, SKYCAM_IRQ },
73 /* SA GMM Device */
74 Package () { 0x0008FFFF, 0, 0, GMM_IRQ },
75 })
77 Name (PICN, Package () {
78 /* D31: cAVS, SMBus, GbE, Nothpeak */
79 Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
80 Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
81 Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
82 Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
83 /* D29: PCI Express Port 9-16 */
84 Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
85 Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
86 Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
87 Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
88 /* D28: PCI Express Port 1-8 */
89 Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
90 Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
91 Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
92 Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
93 /* D27: PCI Express Port 17-20 */
94 Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 },
95 Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 },
96 Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 },
97 Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 },
98 /* D23 */
99 Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
100 /* D22: CSME (HECI, IDE-R, KT redirection */
101 Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
102 Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
103 Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
104 Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
105 /* D20: xHCI, OTG, Thermal, Camera */
106 Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
107 Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
108 Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
109 Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
110 /* P.E.G. Root Port D1F0 */
111 Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
112 Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
113 Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
114 Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
115 /* SA IGFX Device */
116 Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
117 /* SA Thermal Device */
118 Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
119 /* SA Skycam Device */
120 Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
121 /* SA GMM Device */
122 Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
123 })
125 Method (_PRT)
126 {
127 If (PICM) {
128 Return (^PICP)
129 } Else {
130 Return (^PICN)
131 }
132 }