src/soc/intel/quark/chip.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <assert.h>
  16 #include <device/device.h>
  17 #include <romstage_handoff.h>
  18 #include <soc/ramstage.h>
  19 #include <soc/reg_access.h>
  20
  21 /* Cat Trip Clear value must be less than Cat Trip Set value */
  22 #define PLATFORM_CATASTROPHIC_TRIP_CELSIUS      105
  23 #define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS     65
  24
  25 static const struct reg_script thermal_init_script[] = {
  26
  27         /* Setup RMU Thermal sensor registers for Ratiometric mode. */
  28         REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG,
  29                 ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK
  30                         | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK
  31                         | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN
  32                         | B_TSCGF1_CONFIG_IBGEN
  33                         | B_TSCGF1_CONFIG_IBGCHOPEN),
  34                 ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE
  35                         << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP)
  36                 | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE
  37                         << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP)
  38                 | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE
  39                         << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP)
  40                 | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE
  41                         << B_TSCGF1_CONFIG_IBGEN_BP)
  42                 | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE
  43                         << B_TSCGF1_CONFIG_IBGCHOPEN_BP))),
  44
  45         REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2,
  46                 ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK
  47                         | B_TSCGF2_CONFIG2_ISPARECTRL_MASK
  48                         | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK),
  49                 ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE
  50                         << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP)
  51                 | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE
  52                         << B_TSCGF2_CONFIG2_ISPARECTRL_BP)
  53                 | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE
  54                         << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))),
  55
  56         REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG,
  57                 ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK
  58                         | B_TSCGF2_CONFIG_IDSTIMING_MASK),
  59                 ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE
  60                         << B_TSCGF2_CONFIG_IDSCONTROL_BP)
  61                 | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE
  62                         << B_TSCGF2_CONFIG_IDSTIMING_BP))),
  63
  64         REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
  65                 ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK,
  66                 V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE
  67                         << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP),
  68
  69         /* Enable RMU Thermal sensor with a Catastrophic Trip point. */
  70
  71         /* Set up Catastrophic Trip point.
  72         *
  73         * Trip Register fields are 8-bit temperature values of granularity 1
  74         * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds
  75         * to 205 degrees C.
  76         *
  77         * Add 50 to Celsius values to get values for register fields.
  78         */
  79         REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP,
  80                 ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK),
  81                 (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50)
  82                         << TS_CAT_TRIP_SET_THOLD_BP)
  83                 | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50)
  84                         << TS_CAT_TRIP_CLEAR_THOLD_BP))),
  85
  86         /* To enable the TS do the following:
  87          *    1)  Take the TS out of reset by setting itsrst to 0x0.
  88          *    2)  Enable the TS using RMU Thermal sensor mode register.
  89          */
  90         REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
  91                 ~B_TSCGF3_CONFIG_ITSRST),
  92         REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE),
  93
  94         /* Lock all RMU Thermal sensor control & trip point registers. */
  95         REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE
  96                 | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE),
  97         REG_SCRIPT_END
  98 };
  99
 100 static void chip_init(void *chip_info)
 101 {
 102         /* Validate the temperature settings */
 103         ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
 104         ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
 105                 > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS);
 106
 107         /* Set the temperature settings */
 108         reg_script_run(thermal_init_script);
 109
 110         /* Verify that the thermal configuration is locked */
 111         ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG)
 112                 & (TS_LOCK_THRM_CTRL_REGS_ENABLE
 113                         | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE))
 114                 == (TS_LOCK_THRM_CTRL_REGS_ENABLE
 115                         | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
 116
 117         /* Perform silicon specific init. */
 118         fsp_silicon_init(romstage_handoff_is_resume());
 119 }
 120
 121 static void pci_domain_set_resources(struct device *dev)
 122 {
 123         assign_resources(dev->link_list);
 124 }
 125
 126 static struct device_operations pci_domain_ops = {
 127         .read_resources = pci_domain_read_resources,
 128         .set_resources  = pci_domain_set_resources,
 129         .scan_bus       = pci_domain_scan_bus,
 130 };
 131
 132 static void chip_enable_dev(struct device *dev)
 133 {
 134
 135         /* Set the operations if it is a special bus type */
 136         if (dev->path.type == DEVICE_PATH_DOMAIN)
 137                 dev->ops = &pci_domain_ops;
 138 }
 139
 140 struct chip_operations soc_intel_quark_ops = {
 141         CHIP_NAME("Intel Quark")
 142         .init           = &chip_init,
 143         .enable_dev     = chip_enable_dev,
 144 };