src/soc/intel/icelake/smihandler.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <console/console.h>
  16 #include <device/pci_def.h>
  17 #include <intelblocks/cse.h>
  18 #include <intelblocks/smihandler.h>
  19 #include <soc/soc_chip.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pm.h>
  22
  23 /*
  24  * Specific SOC SMI handler during ramstage finalize phase
  25  *
  26  * BIOS can't make CSME function disable as is due to POSTBOOT_SAI
  27  * restriction in place from ICP chipset. Hence create SMI Handler to
  28  * perform CSME function disabling logic during SMM mode.
  29  */
  30 void smihandler_soc_at_finalize(void)
  31 {
  32         const struct soc_intel_icelake_config *config;
  33
  34         config = config_of_soc();
  35
  36         if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
  37                 heci_disable();
  38 }
  39
  40 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
  41         [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
  42         [APM_STS_BIT] = smihandler_southbridge_apmc,
  43         [PM1_STS_BIT] = smihandler_southbridge_pm1,
  44         [GPE0_STS_BIT] = smihandler_southbridge_gpe0,
  45         [GPIO_STS_BIT] = smihandler_southbridge_gpi,
  46         [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
  47         [MCSMI_STS_BIT] = smihandler_southbridge_mc,
  48 #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
  49         [TCO_STS_BIT] = smihandler_southbridge_tco,
  50 #endif
  51         [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
  52         [MONITOR_STS_BIT] = smihandler_southbridge_monitor,
  53 };