src/soc/intel/icelake/include/soc/pm.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef _SOC_PM_H_
  16 #define _SOC_PM_H_
  17
  18 #define PM1_STS                 0x00
  19 #define  WAK_STS                (1 << 15)
  20 #define  PCIEXPWAK_STS          (1 << 14)
  21 #define  PRBTNOR_STS            (1 << 11)
  22 #define  RTC_STS                (1 << 10)
  23 #define  PWRBTN_STS             (1 << 8)
  24 #define  GBL_STS                (1 << 5)
  25 #define  BM_STS                 (1 << 4)
  26 #define  TMROF_STS              (1 << 0)
  27 #define PM1_EN                  0x02
  28 #define  PCIEXPWAK_DIS          (1 << 14)
  29 #define  RTC_EN                 (1 << 10)
  30 #define  PWRBTN_EN              (1 << 8)
  31 #define  GBL_EN                 (1 << 5)
  32 #define  TMROF_EN               (1 << 0)
  33 #define PM1_CNT                 0x04
  34 #define  GBL_RLS                (1 << 2)
  35 #define  BM_RLD                 (1 << 1)
  36 #define  SCI_EN                 (1 << 0)
  37 #define PM1_TMR                 0x08
  38 #define SMI_EN                  0x30
  39 #define  XHCI_SMI_EN            (1 << 31)
  40 #define  ME_SMI_EN              (1 << 30)
  41 #define  ESPI_SMI_EN            (1 << 28)
  42 #define  GPIO_UNLOCK_SMI_EN     (1 << 27)
  43 #define  INTEL_USB2_EN          (1 << 18)
  44 #define  LEGACY_USB2_EN         (1 << 17)
  45 #define  PERIODIC_EN            (1 << 14)
  46 #define  TCO_SMI_EN             (1 << 13)
  47 #define  MCSMI_EN               (1 << 11)
  48 #define  BIOS_RLS               (1 <<  7)
  49 #define  SWSMI_TMR_EN           (1 <<  6)
  50 #define  APMC_EN                (1 <<  5)
  51 #define  SLP_SMI_EN             (1 <<  4)
  52 #define  LEGACY_USB_EN          (1 <<  3)
  53 #define  BIOS_EN                (1 <<  2)
  54 #define  EOS                    (1 <<  1)
  55 #define  GBL_SMI_EN             (1 <<  0)
  56 #define SMI_STS                 0x34
  57 #define  SMI_STS_BITS                   32
  58 #define  XHCI_SMI_STS_BIT               31
  59 #define  ME_SMI_STS_BIT                 30
  60 #define  ESPI_SMI_STS_BIT               28
  61 #define  GPIO_UNLOCK_SMI_STS_BIT        27
  62 #define  SPI_SMI_STS_BIT                26
  63 #define  SCC_SMI_STS_BIT                25
  64 #define  MONITOR_STS_BIT                21
  65 #define  PCI_EXP_SMI_STS_BIT            20
  66 #define  SMBUS_SMI_STS_BIT              16
  67 #define  SERIRQ_SMI_STS_BIT             15
  68 #define  PERIODIC_STS_BIT               14
  69 #define  TCO_STS_BIT                    13
  70 #define  DEVMON_STS_BIT                 12
  71 #define  MCSMI_STS_BIT                  11
  72 #define  GPIO_STS_BIT                   10
  73 #define  GPE0_STS_BIT                   9
  74 #define  PM1_STS_BIT                    8
  75 #define  SWSMI_TMR_STS_BIT              6
  76 #define  APM_STS_BIT                    5
  77 #define  SMI_ON_SLP_EN_STS_BIT          4
  78 #define  LEGACY_USB_STS_BIT             3
  79 #define  BIOS_STS_BIT                   2
  80 #define GPE_CNTL                0x42
  81 #define  SWGPE_CTRL             (1 << 1)
  82 #define DEVACT_STS              0x44
  83 #define PM2_CNT                 0x50
  84
  85 #define GPE0_REG_MAX            4
  86 #define GPE0_REG_SIZE           32
  87 #define GPE0_STS(x)             (0x60 + ((x) * 4))
  88 #define  GPE_31_0               0       /* 0x60/0x70 = GPE[31:0] */
  89 #define  GPE_63_32              1       /* 0x64/0x74 = GPE[63:32] */
  90 #define  GPE_95_64              2       /* 0x68/0x78 = GPE[95:64] */
  91 #define  GPE_STD                3       /* 0x6c/0x7c = Standard GPE */
  92 #define GPE_STS_RSVD            GPE_STD
  93 #define   WADT_STS              (1 << 18)
  94 #define   GPIO_T2_STS           (1 << 15)
  95 #define   ESPI_STS              (1 << 14)
  96 #define   PME_B0_STS            (1 << 13)
  97 #define   ME_SCI_STS            (1 << 12)
  98 #define   PME_STS               (1 << 11)
  99 #define   BATLOW_STS            (1 << 10)
 100 #define   PCI_EXP_STS           (1 << 9)
 101 #define   SMB_WAK_STS           (1 << 7)
 102 #define   TCOSCI_STS            (1 << 6)
 103 #define   SWGPE_STS             (1 << 2)
 104 #define   HOT_PLUG_STS          (1 << 1)
 105 #define GPE0_EN(x)              (0x70 + ((x) * 4))
 106 #define   WADT_EN               (1 << 18)
 107 #define   GPIO_T2_EN            (1 << 15)
 108 #define   ESPI_EN               (1 << 14)
 109 #define   PME_B0_EN_BIT         13
 110 #define   PME_B0_EN             (1 << PME_B0_EN_BIT)
 111 #define   ME_SCI_EN             (1 << 12)
 112 #define   PME_EN                (1 << 11)
 113 #define   BATLOW_EN             (1 << 10)
 114 #define   PCI_EXP_EN            (1 << 9)
 115 #define   TCOSCI_EN             (1 << 6)
 116 #define   SWGPE_EN              (1 << 2)
 117 #define   HOT_PLUG_EN           (1 << 1)
 118
 119 #define EN_BLOCK                3
 120
 121 /*
 122  * Enable SMI generation:
 123  *  - on APMC writes (io 0xb2)
 124  *  - on writes to SLP_EN (sleep states)
 125  *  - on writes to GBL_RLS (bios commands)
 126  *  - on eSPI events (does nothing on LPC systems)
 127  * No SMIs:
 128  *  - on TCO events, unless enabled in common code
 129  *  - on microcontroller writes (io 0x62/0x66)
 130  */
 131 #define ENABLE_SMI_PARAMS \
 132         (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)
 133
 134 #define PSS_RATIO_STEP          2
 135 #define PSS_MAX_ENTRIES         8
 136 #define PSS_LATENCY_TRANSITION  10
 137 #define PSS_LATENCY_BUSMASTER   10
 138
 139 #if !defined(__ACPI__)
 140
 141 #include <arch/acpi.h>
 142 #include <soc/gpe.h>
 143 #include <soc/iomap.h>
 144 #include <soc/smbus.h>
 145 #include <soc/pmc.h>
 146
 147 struct chipset_power_state {
 148         uint16_t pm1_sts;
 149         uint16_t pm1_en;
 150         uint32_t pm1_cnt;
 151         uint16_t tco1_sts;
 152         uint16_t tco2_sts;
 153         uint32_t gpe0_sts[4];
 154         uint32_t gpe0_en[4];
 155         uint32_t gen_pmcon_a;
 156         uint32_t gen_pmcon_b;
 157         uint32_t gblrst_cause[2];
 158         uint32_t prev_sleep_state;
 159 } __packed;
 160
 161 /* Get base address PMC memory mapped registers. */
 162 uint8_t *pmc_mmio_regs(void);
 163
 164 /* Get base address of TCO I/O registers. */
 165 uint16_t smbus_tco_regs(void);
 166
 167 /* Set the DISB after DRAM init */
 168 void pmc_set_disb(void);
 169
 170 /* Clear PMCON status bits */
 171 void pmc_clear_pmcon_sts(void);
 172
 173 /* STM Support */
 174 uint16_t get_pmbase(void);
 175
 176 #endif /* !defined(__ACPI__) */
 177 #endif