src/soc/intel/denverton_ns/upd_display.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <fsp/util.h>
  18 #include <lib.h>
  19
  20 /* Display the UPD parameters for MemoryInit */
  21 void soc_display_fspm_upd_params(
  22         const FSPM_UPD *fspm_old_upd,
  23         const FSPM_UPD *fspm_new_upd)
  24 {
  25         const FSP_M_CONFIG *new;
  26         const FSP_M_CONFIG *old;
  27
  28         old = &fspm_old_upd->FspmConfig;
  29         new = &fspm_new_upd->FspmConfig;
  30
  31         printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
  32
  33         #define DISPLAY_UPD(field) \
  34                 fsp_display_upd_value(#field, sizeof(old->field), \
  35                         old->field, new->field)
  36
  37         DISPLAY_UPD(PcdSmmTsegSize);
  38         DISPLAY_UPD(PcdFspDebugPrintErrorLevel);
  39         DISPLAY_UPD(PcdSpdSmbusAddress_0_0);
  40         DISPLAY_UPD(PcdSpdSmbusAddress_0_1);
  41         DISPLAY_UPD(PcdSpdSmbusAddress_1_0);
  42         DISPLAY_UPD(PcdSpdSmbusAddress_1_1);
  43         DISPLAY_UPD(PcdMrcRmtSupport);
  44         DISPLAY_UPD(PcdMrcRmtCpgcExpLoopCntValue);
  45         DISPLAY_UPD(PcdMrcRmtCpgcNumBursts);
  46         DISPLAY_UPD(PcdMemoryPreservation);
  47         DISPLAY_UPD(PcdFastBoot);
  48         DISPLAY_UPD(PcdEccSupport);
  49         DISPLAY_UPD(PcdHsuartDevice);
  50         DISPLAY_UPD(PcdMemoryDown);
  51         DISPLAY_UPD(PcdEnableSATA0);
  52         DISPLAY_UPD(PcdEnableSATA1);
  53         DISPLAY_UPD(PcdEnableIQAT);
  54         DISPLAY_UPD(PcdSmbusSpdWriteDisable);
  55         DISPLAY_UPD(PcdEnableMeShutdown);
  56         DISPLAY_UPD(PcdEnableXhci);
  57         DISPLAY_UPD(PcdDdrFreq);
  58         DISPLAY_UPD(PcdMmioSize);
  59         DISPLAY_UPD(PcdMeHeciCommunication);
  60         DISPLAY_UPD(PcdHsioLanesNumber);
  61         DISPLAY_UPD(PcdFiaMuxConfigPtr);
  62         DISPLAY_UPD(PcdHalfWidthEnable);
  63         DISPLAY_UPD(PcdTclIdle);
  64         DISPLAY_UPD(PcdInterleaveMode);
  65         DISPLAY_UPD(PcdMemoryThermalThrottling);
  66         DISPLAY_UPD(PcdSkipMemoryTest);
  67         DISPLAY_UPD(PcdUsb2Port1Pin);
  68         DISPLAY_UPD(PcdUsb2Port2Pin);
  69         DISPLAY_UPD(PcdUsb2Port3Pin);
  70         DISPLAY_UPD(PcdUsb2Port4Pin);
  71         DISPLAY_UPD(PcdUsb3Port1Pin);
  72         DISPLAY_UPD(PcdUsb3Port2Pin);
  73         DISPLAY_UPD(PcdUsb3Port3Pin);
  74         DISPLAY_UPD(PcdUsb3Port4Pin);
  75         DISPLAY_UPD(PcdIOxAPIC0_199);
  76         DISPLAY_UPD(PcdDmapX16);
  77
  78         #undef DISPLAY_UPD
  79
  80         hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
  81 }
  82
  83 /* Display the UPD parameters for SiliconInit */
  84 void soc_display_fsps_upd_params(
  85         const FSPS_UPD *fsps_old_upd,
  86         const FSPS_UPD *fsps_new_upd)
  87 {
  88         const FSP_S_CONFIG *new;
  89         const FSP_S_CONFIG *old;
  90
  91         old = &fsps_old_upd->FspsConfig;
  92         new = &fsps_new_upd->FspsConfig;
  93
  94         printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
  95
  96         #define DISPLAY_UPD(field) \
  97                 fsp_display_upd_value(#field, sizeof(old->field), \
  98                         old->field, new->field)
  99
 100         DISPLAY_UPD(PcdBifurcationPcie0);
 101         DISPLAY_UPD(PcdBifurcationPcie1);
 102         DISPLAY_UPD(PcdActiveCoreCount);
 103         DISPLAY_UPD(PcdCpuMicrocodePatchBase);
 104         DISPLAY_UPD(PcdCpuMicrocodePatchSize);
 105         DISPLAY_UPD(PcdEnablePcie0);
 106         DISPLAY_UPD(PcdEnablePcie1);
 107         DISPLAY_UPD(PcdEnableEmmc);
 108         DISPLAY_UPD(PcdEnableGbE);
 109         DISPLAY_UPD(PcdFiaMuxConfigRequestPtr);
 110         DISPLAY_UPD(PcdPcieRootPort0DeEmphasis);
 111         DISPLAY_UPD(PcdPcieRootPort1DeEmphasis);
 112         DISPLAY_UPD(PcdPcieRootPort2DeEmphasis);
 113         DISPLAY_UPD(PcdPcieRootPort3DeEmphasis);
 114         DISPLAY_UPD(PcdPcieRootPort4DeEmphasis);
 115         DISPLAY_UPD(PcdPcieRootPort5DeEmphasis);
 116         DISPLAY_UPD(PcdPcieRootPort6DeEmphasis);
 117         DISPLAY_UPD(PcdPcieRootPort7DeEmphasis);
 118         DISPLAY_UPD(PcdEMMCDLLConfigPtr);
 119         DISPLAY_UPD(PcdPcieRootPort0LinkSpeed);
 120         DISPLAY_UPD(PcdPcieRootPort1LinkSpeed);
 121         DISPLAY_UPD(PcdPcieRootPort2LinkSpeed);
 122         DISPLAY_UPD(PcdPcieRootPort3LinkSpeed);
 123         DISPLAY_UPD(PcdPcieRootPort4LinkSpeed);
 124         DISPLAY_UPD(PcdPcieRootPort5LinkSpeed);
 125         DISPLAY_UPD(PcdPcieRootPort6LinkSpeed);
 126         DISPLAY_UPD(PcdPcieRootPort7LinkSpeed);
 127         DISPLAY_UPD(PcdPcieRootPort0Aspm);
 128         DISPLAY_UPD(PcdPcieRootPort1Aspm);
 129         DISPLAY_UPD(PcdPcieRootPort2Aspm);
 130         DISPLAY_UPD(PcdPcieRootPort3Aspm);
 131         DISPLAY_UPD(PcdPcieRootPort4Aspm);
 132         DISPLAY_UPD(PcdPcieRootPort5Aspm);
 133         DISPLAY_UPD(PcdPcieRootPort6Aspm);
 134         DISPLAY_UPD(PcdPcieRootPort7Aspm);
 135
 136         #undef DISPLAY_UPD
 137
 138         hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
 139 }