src/soc/intel/denverton_ns/systemagent.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <cbmem.h>
  16 #include <console/console.h>
  17 #include <device/mmio.h>
  18 #include <device/pci_ops.h>
  19 #include <stdint.h>
  20 #include <delay.h>
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <device/pci_ids.h>
  24 #include <timer.h>
  25
  26 #include <soc/iomap.h>
  27 #include <soc/pci_devs.h>
  28 #include <soc/ramstage.h>
  29 #include <soc/systemagent.h>
  30
  31 #define _1ms 1
  32 #define WAITING_STEP 100
  33
  34 static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
  35                         u32 *len)
  36 {
  37         u32 pciexbar_reg;
  38
  39         *base = 0;
  40         *len = 0;
  41
  42         pciexbar_reg = pci_read_config32(dev, index);
  43
  44         if (!(pciexbar_reg & (1 << 0)))
  45                 return 0;
  46
  47         switch ((pciexbar_reg >> 1) & 3) {
  48         case 0: /* 256MB */
  49                 *base = pciexbar_reg &
  50                         ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28));
  51                 *len = 256 * 1024 * 1024;
  52                 return 1;
  53         case 1: /* 128M */
  54                 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
  55                                         (1 << 28) | (1 << 27));
  56                 *len = 128 * 1024 * 1024;
  57                 return 1;
  58         case 2: /* 64M */
  59                 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
  60                                         (1 << 28) | (1 << 27) | (1 << 26));
  61                 *len = 64 * 1024 * 1024;
  62                 return 1;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
  69 {
  70         u32 bar;
  71
  72         bar = pci_read_config32(dev, index);
  73
  74         /* If not enabled don't report it. */
  75         if (!(bar & 0x1))
  76                 return 0;
  77
  78         /* Knock down the enable bit. */
  79         *base = bar & ~1;
  80
  81         return 1;
  82 }
  83
  84 struct fixed_mmio_descriptor {
  85         unsigned int index;
  86         u32 size;
  87         int (*get_resource)(struct device *dev, unsigned int index, u32 *base,
  88                             u32 *size);
  89         const char *description;
  90 };
  91
  92 struct fixed_mmio_descriptor mc_fixed_resources[] = {
  93         {PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR"},
  94         {MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR"},
  95 };
  96
  97 /*
  98  * Add all known fixed MMIO ranges that hang off the host bridge/memory
  99  * controller device.
 100  */
 101 static void mc_add_fixed_mmio_resources(struct device *dev)
 102 {
 103         int i;
 104
 105         for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
 106                 u32 base;
 107                 u32 size;
 108                 struct resource *resource;
 109                 unsigned int index;
 110
 111                 size = mc_fixed_resources[i].size;
 112                 index = mc_fixed_resources[i].index;
 113                 if (!mc_fixed_resources[i].get_resource(dev, index, &base,
 114                                                         &size))
 115                         continue;
 116
 117                 resource = new_resource(dev, mc_fixed_resources[i].index);
 118                 resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 119                                   IORESOURCE_STORED | IORESOURCE_RESERVE |
 120                                   IORESOURCE_ASSIGNED;
 121                 resource->base = base;
 122                 resource->size = size;
 123                 printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
 124                        __func__, mc_fixed_resources[i].description, index,
 125                        (unsigned long)base, (unsigned long)(base + size - 1));
 126         }
 127 }
 128
 129 struct map_entry {
 130         int reg;
 131         int is_64_bit;
 132         int is_limit;
 133         const char *description;
 134 };
 135
 136 static void read_map_entry(struct device *dev, struct map_entry *entry,
 137                            uint64_t *result)
 138 {
 139         uint64_t value;
 140         uint64_t mask;
 141
 142         /* All registers are on a 1MiB granularity. */
 143         mask = ((1ULL << 20) - 1);
 144         mask = ~mask;
 145
 146         value = 0;
 147
 148         if (entry->is_64_bit) {
 149                 value = pci_read_config32(dev, entry->reg + 4);
 150                 value <<= 32;
 151         }
 152
 153         value |= (uint64_t)pci_read_config32(dev, entry->reg);
 154         value &= mask;
 155
 156         if (entry->is_limit)
 157                 value |= ~mask;
 158
 159         *result = value;
 160 }
 161
 162 #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_)                        \
 163         {                                                                \
 164                 .reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_, \
 165                 .description = desc_,                                    \
 166         }
 167
 168 #define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_)
 169 #define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_)
 170 #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_)
 171
 172 enum {
 173         TOUUD_REG,
 174         TOLUD_REG,
 175         TSEG_REG,
 176         /* Must be last. */
 177         NUM_MAP_ENTRIES
 178 };
 179
 180 static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
 181                 [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
 182                 [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
 183                 [TSEG_REG] = MAP_ENTRY_BASE_32(TSEGMB, "TSEGMB"),
 184 };
 185
 186 static void mc_read_map_entries(struct device *dev, uint64_t *values)
 187 {
 188         int i;
 189         for (i = 0; i < NUM_MAP_ENTRIES; i++)
 190                 read_map_entry(dev, &memory_map[i], &values[i]);
 191 }
 192
 193 static void mc_report_map_entries(struct device *dev, uint64_t *values)
 194 {
 195         int i;
 196         for (i = 0; i < NUM_MAP_ENTRIES; i++) {
 197                 printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
 198                        memory_map[i].description, values[i]);
 199         }
 200 }
 201
 202 static void mc_add_dram_resources(struct device *dev)
 203 {
 204         unsigned long base_k, size_k;
 205         unsigned long touud_k;
 206         unsigned long index;
 207         struct resource *resource;
 208         uint64_t mc_values[NUM_MAP_ENTRIES];
 209         uintptr_t top_of_ram;
 210
 211         /* Read in the MAP registers and report their values. */
 212         mc_read_map_entries(dev, &mc_values[0]);
 213         mc_report_map_entries(dev, &mc_values[0]);
 214
 215         /*
 216          * These are the host memory ranges that should be added:
 217          * - 0 -> 0xa0000: cacheable
 218          * - 0xc0000 -> 0x100000 : reserved
 219          * - 0x100000 -> top_of_ram : cacheable
 220          * - top_of_ram -> TSEG: uncacheable
 221          * - TESG -> TOLUD: cacheable with standard MTRRs and reserved
 222          * - 4GiB -> TOUUD: cacheable
 223          *
 224          * The default SMRAM space is reserved so that the range doesn't
 225          * have to be saved during S3 Resume. Once marked reserved the OS
 226          * cannot use the memory. This is a bit of an odd place to reserve
 227          * the region, but the CPU devices don't have dev_ops->read_resources()
 228          * called on them.
 229          *
 230          * The range 0xa0000 -> 0xc0000 does not have any resources
 231          * associated with it to handle legacy VGA memory. If this range
 232          * is not omitted the mtrr code will setup the area as cacheable
 233          * causing VGA access to not work.
 234          *
 235          * The TSEG region is mapped as cacheable so that one can perform
 236          * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
 237          * precedence over the existing MTRRs covering this region.
 238          *
 239          * It should be noted that cacheable entry types need to be added in
 240          * order. The reason is that the current MTRR code assumes this and
 241          * falls over itself if it isn't.
 242          *
 243          * The resource index starts low and should not meet or exceed
 244          * PCI_BASE_ADDRESS_0.
 245          */
 246         index = 0;
 247         top_of_ram = (uintptr_t)cbmem_top();
 248
 249         /* 0 - > 0xa0000 */
 250         base_k = 0;
 251         size_k = (0xa0000 >> 10) - base_k;
 252         ram_resource(dev, index++, base_k, size_k);
 253
 254         /* 0x100000 -> top_of_ram */
 255         base_k = 0x100000 >> 10;
 256         size_k = (top_of_ram >> 10) - base_k;
 257         ram_resource(dev, index++, base_k, size_k);
 258
 259         /* top_of_ram -> TSEG */
 260         resource = new_resource(dev, index++);
 261         resource->base = top_of_ram;
 262         resource->size = mc_values[TSEG_REG] - resource->base;
 263         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 264                           IORESOURCE_STORED | IORESOURCE_RESERVE |
 265                           IORESOURCE_ASSIGNED;
 266
 267         /* TSEG -> TOLUD */
 268         resource = new_resource(dev, index++);
 269         resource->base = mc_values[TSEG_REG];
 270         resource->size = mc_values[TOLUD_REG] - resource->base;
 271         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 272                           IORESOURCE_STORED | IORESOURCE_RESERVE |
 273                           IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
 274         printk(BIOS_DEBUG,
 275                 "SMM memory location: 0x%llx  SMM memory size: 0x%llx\n",
 276                 resource->base, resource->size);
 277
 278         /* 4GiB -> TOUUD */
 279         base_k = 4096 * 1024; /* 4GiB */
 280         touud_k = mc_values[TOUUD_REG] >> 10;
 281         size_k = touud_k - base_k;
 282         if (touud_k > base_k)
 283                 ram_resource(dev, index++, base_k, size_k);
 284
 285         /*
 286          * Reserve everything between A segment and 1MB:
 287          *
 288          * 0xa0000 - 0xbffff: legacy VGA
 289          * 0xc0000 - 0xfffff: reserved RAM
 290          */
 291         mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
 292         reserved_ram_resource(dev, index++, (0xc0000 >> 10),
 293                               (0x100000 - 0xc0000) >> 10);
 294 }
 295
 296 static void systemagent_read_resources(struct device *dev)
 297 {
 298         /* Read standard PCI resources. */
 299         pci_dev_read_resources(dev);
 300
 301         /* Add all fixed MMIO resources. */
 302         mc_add_fixed_mmio_resources(dev);
 303
 304         /* Calculate and add DRAM resources. */
 305         mc_add_dram_resources(dev);
 306 }
 307
 308 static void systemagent_init(struct device *dev)
 309 {
 310         struct stopwatch sw;
 311         void *bios_reset_cpl =
 312                 (void *)(DEFAULT_MCHBAR + MCH_BAR_BIOS_RESET_CPL);
 313         uint32_t reg = read32(bios_reset_cpl);
 314
 315         /* Stage0 BIOS Reset Complete (RST_CPL) */
 316         reg |= RST_CPL_BIT;
 317         write32(bios_reset_cpl, reg);
 318
 319         /*
 320         * Poll for bit 8 in same reg (RST_CPL).
 321         * We wait here till 1 ms for the bit to get set.
 322         */
 323         stopwatch_init_msecs_expire(&sw, _1ms);
 324         while (!(read32(bios_reset_cpl) & PCODE_INIT_DONE)) {
 325                 if (stopwatch_expired(&sw)) {
 326                         printk(BIOS_DEBUG, "Failed to set RST_CPL bit\n");
 327                         return;
 328                 }
 329                 udelay(WAITING_STEP);
 330         }
 331         printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
 332 }
 333
 334 static struct device_operations systemagent_ops = {
 335         .read_resources = systemagent_read_resources,
 336         .set_resources = pci_dev_set_resources,
 337         .enable_resources = pci_dev_enable_resources,
 338         .init = systemagent_init,
 339         .ops_pci = &soc_pci_ops,
 340 };
 341
 342 /* IDs for System Agent device of Intel Denverton SoC */
 343 static const unsigned short systemagent_ids[] = {
 344         PCI_DEVICE_ID_INTEL_DENVERTON_SA,
 345         PCI_DEVICE_ID_INTEL_DENVERTONAD_SA,
 346         0
 347 };
 348
 349 static const struct pci_driver systemagent_driver __pci_driver = {
 350         .ops = &systemagent_ops,
 351         .vendor = PCI_VENDOR_ID_INTEL,
 352         .devices = systemagent_ids
 353 };