src/soc/intel/denverton_ns/soc_util.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <stdint.h>
  17 #include <device/mmio.h>
  18 #include <device/pci_ops.h>
  19 #include <device/pci.h>
  20 #include <device/pci_def.h>
  21 #include <device/device.h>
  22 #include <string.h>
  23 #include <soc/iomap.h>
  24 #include <soc/soc_util.h>
  25 #include <soc/pmc.h>
  26 #include <soc/smbus.h>
  27 #include <soc/lpc.h>
  28 #include <soc/pci_devs.h>
  29 #include <soc/systemagent.h>
  30
  31 #ifdef __SIMPLE_DEVICE__
  32 pci_devfn_t get_hostbridge_dev(void)
  33 {
  34         return PCI_DEV(0, SA_DEV, SA_FUNC);
  35 }
  36 #else
  37 struct device *get_hostbridge_dev(void)
  38 {
  39         return pcidev_on_root(SA_DEV, SA_FUNC);
  40 }
  41 #endif
  42
  43 #ifdef __SIMPLE_DEVICE__
  44 pci_devfn_t get_lpc_dev(void)
  45 {
  46         return PCI_DEV(0, LPC_DEV, LPC_FUNC);
  47 }
  48 #else
  49 struct device *get_lpc_dev(void)
  50 {
  51         return pcidev_on_root(LPC_DEV, LPC_FUNC);
  52 }
  53 #endif
  54
  55 #ifdef __SIMPLE_DEVICE__
  56 pci_devfn_t get_pmc_dev(void)
  57 {
  58         return PCI_DEV(0, PMC_DEV, PMC_FUNC);
  59 }
  60 #else
  61 struct device *get_pmc_dev(void)
  62 {
  63         return pcidev_on_root(PMC_DEV, PMC_FUNC);
  64 }
  65 #endif
  66
  67 #ifdef __SIMPLE_DEVICE__
  68 pci_devfn_t get_smbus_dev(void)
  69 {
  70         return PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
  71 }
  72 #else
  73 struct device *get_smbus_dev(void)
  74 {
  75         return pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
  76 }
  77 #endif
  78
  79 uint32_t get_pciebase(void)
  80 {
  81 #ifdef __SIMPLE_DEVICE__
  82         pci_devfn_t dev;
  83 #else
  84         struct device *dev;
  85 #endif
  86         u32 pciexbar_reg;
  87
  88         dev = get_hostbridge_dev();
  89         if (!dev)
  90                 return 0;
  91
  92         pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
  93
  94         if (!(pciexbar_reg & (1 << 0)))
  95                 return 0;
  96
  97         switch (pciexbar_reg & MASK_PCIEXBAR_LENGTH) {
  98         case MASK_PCIEXBAR_LENGTH_256M:
  99                 pciexbar_reg &= MASK_PCIEXBAR_256M;
 100                 break;
 101         case MASK_PCIEXBAR_LENGTH_128M:
 102                 pciexbar_reg &= MASK_PCIEXBAR_128M;
 103                 break;
 104         case MASK_PCIEXBAR_LENGTH_64M:
 105                 pciexbar_reg &= MASK_PCIEXBAR_64M;
 106                 break;
 107         default:
 108                 pciexbar_reg &= MASK_PCIEXBAR_256M;
 109                 break;
 110         }
 111
 112         return pciexbar_reg;
 113 }
 114
 115 uint32_t get_pcielength(void)
 116 {
 117 #ifdef __SIMPLE_DEVICE__
 118         pci_devfn_t dev;
 119 #else
 120         struct device *dev;
 121 #endif
 122         u32 pciexbar_reg;
 123
 124         dev = get_hostbridge_dev();
 125         if (!dev)
 126                 return 0;
 127
 128         pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
 129
 130         if (!(pciexbar_reg & (1 << 0)))
 131                 return 0;
 132
 133         switch (pciexbar_reg & MASK_PCIEXBAR_LENGTH) {
 134         case MASK_PCIEXBAR_LENGTH_256M:
 135                 pciexbar_reg = 256;
 136                 break;
 137         case MASK_PCIEXBAR_LENGTH_128M:
 138                 pciexbar_reg = 128;
 139                 break;
 140         case MASK_PCIEXBAR_LENGTH_64M:
 141                 pciexbar_reg = 64;
 142                 break;
 143         default:
 144                 pciexbar_reg = 64;
 145                 break;
 146         }
 147
 148         return pciexbar_reg;
 149 }
 150
 151 uint32_t get_tseg_memory(void)
 152 {
 153 #ifdef __SIMPLE_DEVICE__
 154         pci_devfn_t dev;
 155 #else
 156         struct device *dev;
 157 #endif
 158         dev = get_hostbridge_dev();
 159
 160         if (!dev)
 161                 return 0;
 162
 163         return pci_read_config32(dev, TSEGMB) & MASK_TSEGMB;
 164 }
 165
 166 uint32_t get_top_of_low_memory(void)
 167 {
 168 #ifdef __SIMPLE_DEVICE__
 169         pci_devfn_t dev;
 170 #else
 171         struct device *dev;
 172 #endif
 173         dev = get_hostbridge_dev();
 174
 175         if (!dev)
 176                 return 0;
 177
 178         return pci_read_config32(dev, TOLUD) & MASK_TOLUD;
 179 }
 180
 181 uint64_t get_top_of_upper_memory(void)
 182 {
 183 #ifdef __SIMPLE_DEVICE__
 184         pci_devfn_t dev;
 185 #else
 186         struct device *dev;
 187 #endif
 188         dev = get_hostbridge_dev();
 189
 190         if (!dev)
 191                 return 0;
 192
 193         return ((uint64_t)(pci_read_config32(dev, TOUUD_HI) & MASK_TOUUD_HI)
 194                 << 32) +
 195                (uint64_t)(pci_read_config32(dev, TOUUD_LO) & MASK_TOUUD_LO);
 196 }
 197
 198 uint16_t get_pmbase(void)
 199 {
 200 #ifdef __SIMPLE_DEVICE__
 201         pci_devfn_t dev;
 202 #else
 203         struct device *dev;
 204 #endif
 205         dev = get_pmc_dev();
 206
 207         if (!dev)
 208                 return 0;
 209
 210         return pci_read_config16(dev, PMC_ACPI_BASE) & 0xfff8;
 211 }
 212
 213 uint16_t get_tcobase(void)
 214 {
 215 #ifdef __SIMPLE_DEVICE__
 216         pci_devfn_t dev;
 217 #else
 218         struct device *dev;
 219 #endif
 220         dev = get_smbus_dev();
 221
 222         if (!dev)
 223                 return 0;
 224
 225         return pci_read_config16(dev, TCOBASE) & MASK_TCOBASE;
 226 }
 227
 228 void mmio_andthenor32(void *addr, uint32_t val2and, uint32_t val2or)
 229 {
 230         uint32_t reg32;
 231
 232         reg32 = read32(addr);
 233         reg32 &= (uint32_t)val2and;
 234         reg32 |= (uint32_t)val2or;
 235         write32(addr, reg32);
 236 }
 237
 238 uint8_t silicon_stepping(void)
 239 {
 240         uint8_t revision_id;
 241 #ifdef __SIMPLE_DEVICE__
 242         pci_devfn_t dev;
 243 #else
 244         struct device *dev;
 245 #endif
 246         dev = get_lpc_dev();
 247
 248         if (!dev)
 249                 return 0;
 250
 251         revision_id = pci_read_config8(dev, PCI_REVISION_ID);
 252
 253         return revision_id;
 254 }
 255
 256 void *memcpy_s(void *dest, const void *src, size_t n)
 257 {
 258         uint8_t *dp;
 259         const uint8_t *sp;
 260
 261         dp = (uint8_t *)dest;
 262         sp = (uint8_t *)src;
 263
 264         if (!n)
 265                 return dest;
 266
 267         if (n > UINT32_MAX)
 268                 return dest;
 269
 270         if (!dp)
 271                 return dest;
 272
 273         if (!sp)
 274                 return dest;
 275
 276         /*
 277          * overlap is undefined behavior, do not allow
 278          */
 279         if (((dp > sp) && (dp < (sp + n))) || ((sp > dp) && (sp < (dp + n))))
 280                 return dest;
 281
 282         /*
 283          * now perform the copy
 284          */
 285
 286         /* Original memcpy() function */
 287         unsigned long d0, d1, d2;
 288
 289         asm volatile(
 290 #ifdef __x86_64__
 291                 "rep ; movsd\n\t"
 292                 "mov %4,%%rcx\n\t"
 293 #else
 294                 "rep ; movsl\n\t"
 295                 "movl %4,%%ecx\n\t"
 296 #endif
 297                 "rep ; movsb\n\t"
 298                 : "=&c"(d0), "=&D"(d1), "=&S"(d2)
 299                 : "0"(n >> 2), "g"(n & 3), "1"(dest), "2"(src)
 300                 : "memory");
 301
 302         return dest;
 303 }