src/soc/intel/denverton_ns/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <intelblocks/gpio.h>
  17 #include <intelblocks/pcr.h>
  18 #include <soc/pcr.h>
  19 #include <soc/pm.h>
  20
  21 static const struct reset_mapping rst_map[] = {
  22         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  23         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  24         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  25         /* (applicable only for GPD group) */
  26         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
  27 };
  28
  29 static const struct pad_group dnv_community_nc_groups[] = {
  30         INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ3_N),
  31         INTEL_GPP(NORTH_ALL_GBE0_SDP0, NORTH_ALL_PCIE_CLKREQ4_N, NORTH_ALL_MEMHOT_N),
  32 };
  33
  34 static const struct pad_group dnv_community_sc_dfx_groups[] = {
  35         INTEL_GPP(SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT_CLK0, SOUTH_DFX_DFX_PORT15),
  36 };
  37
  38 static const struct pad_group dnv_community_sc0_groups[] = {
  39         INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA0_LED_N),
  40         INTEL_GPP(SOUTH_GROUP0_SMB3_CLTT_DATA, SOUTH_GROUP0_SATA1_LED_N, SOUTH_GROUP0_DFX_SPARE4),
  41 };
  42
  43 static const struct pad_group dnv_community_sc1_groups[] = {
  44         INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_STROBE),
  45         INTEL_GPP(SOUTH_GROUP1_SUSPWRDNACK, SOUTH_GROUP1_EMMC_CLK, SOUTH_GROUP1_GPIO_3),
  46 };
  47
  48 static const struct pad_community dnv_gpio_communities[] = {
  49         {
  50                 .port = PID_GPIOCOM1,
  51                 .first_pad = SOUTH_GROUP1_SUSPWRDNACK,
  52                 .last_pad = SOUTH_GROUP1_GPIO_3,
  53                 .num_gpi_regs = NUM_SC1_GPI_REGS,
  54                 .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +
  55                                      NUM_SC0_GPI_REGS,
  56                 .pad_cfg_base = R_PCH_PCR_GPIO_SC1_PADCFG_OFFSET,
  57                 .host_own_reg_0 = R_PCH_PCR_GPIO_SC1_PAD_OWN,
  58                 .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IS,
  59                 .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_IE,
  60                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_STS,
  61                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC1_GPI_GPE_EN,
  62                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  63                 .name = "GPIO_GPE_SC1",
  64                 .acpi_path = "\\_SB.GPO3",
  65                 .reset_map = rst_map,
  66                 .num_reset_vals = ARRAY_SIZE(rst_map),
  67                 .groups = dnv_community_sc1_groups,
  68                 .num_groups = ARRAY_SIZE(dnv_community_sc1_groups),
  69         }, {
  70                 .port = PID_GPIOCOM1,
  71                 .first_pad = SOUTH_GROUP0_SMB3_CLTT_DATA,
  72                 .last_pad = SOUTH_GROUP0_DFX_SPARE4,
  73                 .num_gpi_regs = NUM_SC0_GPI_REGS,
  74                 .gpi_status_offset = NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS,
  75                 .pad_cfg_base = R_PCH_PCR_GPIO_SC0_PADCFG_OFFSET,
  76                 .host_own_reg_0 = R_PCH_PCR_GPIO_SC0_PAD_OWN,
  77                 .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IS,
  78                 .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_IE,
  79                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_STS,
  80                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC0_GPI_GPE_EN,
  81                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  82                 .name = "GPIO_GPE_SC0",
  83                 .acpi_path = "\\_SB.GPO2",
  84                 .reset_map = rst_map,
  85                 .num_reset_vals = ARRAY_SIZE(rst_map),
  86                 .groups = dnv_community_sc0_groups,
  87                 .num_groups = ARRAY_SIZE(dnv_community_sc0_groups),
  88         }, {
  89                 .port = PID_GPIOCOM1,
  90                 .first_pad = SOUTH_DFX_DFX_PORT_CLK0,
  91                 .last_pad = SOUTH_DFX_DFX_PORT15,
  92                 .num_gpi_regs = NUM_SC_DFX_GPI_REGS,
  93                 .gpi_status_offset = NUM_NC_GPI_REGS,
  94                 .pad_cfg_base = R_PCH_PCR_GPIO_SC_DFX_PADCFG_OFFSET,
  95                 .host_own_reg_0 = R_PCH_PCR_GPIO_SC_DFX_HOSTSW_OWN,
  96                 .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IS,
  97                 .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_IE,
  98                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_STS,
  99                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_SC_DFX_GPI_GPE_EN,
 100                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 101                 .name = "GPIO_GPE_SC_DFX",
 102                 .acpi_path = "\\_SB.GPO1",
 103                 .reset_map = rst_map,
 104                 .num_reset_vals = ARRAY_SIZE(rst_map),
 105                 .groups = dnv_community_sc_dfx_groups,
 106                 .num_groups = ARRAY_SIZE(dnv_community_sc_dfx_groups),
 107         }, {
 108                 .port = PID_GPIOCOM0,
 109                 .first_pad = NORTH_ALL_GBE0_SDP0,
 110                 .last_pad = NORTH_ALL_MEMHOT_N,
 111                 .num_gpi_regs = NUM_NC_GPI_REGS,
 112                 .gpi_status_offset = 0,
 113                 .pad_cfg_base = R_PCH_PCR_GPIO_NC_PADCFG_OFFSET,
 114                 .host_own_reg_0 = R_PCH_PCR_GPIO_NC_PAD_OWN,
 115                 .gpi_int_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IS,
 116                 .gpi_int_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_IE,
 117                 .gpi_smi_sts_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_STS,
 118                 .gpi_smi_en_reg_0 = R_PCH_PCR_GPIO_NC_GPI_GPE_EN,
 119                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 120                 .name = "GPIO_GPE_NC",
 121                 .acpi_path = "\\_SB.GPO0",
 122                 .reset_map = rst_map,
 123                 .num_reset_vals = ARRAY_SIZE(rst_map),
 124                 .groups = dnv_community_nc_groups,
 125                 .num_groups = ARRAY_SIZE(dnv_community_nc_groups),
 126         }
 127 };
 128
 129 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 130 {
 131         *num_communities = ARRAY_SIZE(dnv_gpio_communities);
 132         return dnv_gpio_communities;
 133 }