src/soc/intel/common/block/uart/uart.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/acpi.h>
  16 #include <cbmem.h>
  17 #include <console/uart.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <device/pci_def.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ops.h>
  23 #include <intelblocks/lpss.h>
  24 #include <intelblocks/uart.h>
  25 #include <soc/pci_devs.h>
  26 #include <soc/iomap.h>
  27 #include <soc/nvs.h>
  28
  29 #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
  30 #define UART_CONSOLE_INVALID_INDEX      0xFF
  31
  32 extern const struct uart_gpio_pad_config uart_gpio_pads[];
  33 extern const int uart_max_index;
  34
  35 static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr)
  36 {
  37         /* Ensure controller is in D0 state */
  38         lpss_set_power_state(dev, STATE_D0);
  39
  40         /* Take UART out of reset */
  41         lpss_reset_release(baseaddr);
  42
  43         /* Set M and N divisor inputs and enable clock */
  44         lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL,
  45                         CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
  46 }
  47
  48 #if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)
  49 uintptr_t uart_platform_base(int idx)
  50 {
  51         if (idx == CONFIG_UART_FOR_CONSOLE)
  52                 return CONFIG_CONSOLE_UART_BASE_ADDRESS;
  53         return 0;
  54 }
  55 #endif
  56
  57 static int uart_get_valid_index(void)
  58 {
  59         int index;
  60
  61         for (index = 0; index < uart_max_index; index++) {
  62                 if (uart_gpio_pads[index].console_index ==
  63                                 CONFIG_UART_FOR_CONSOLE)
  64                         return index;
  65         }
  66         /* For valid index, code should not reach here */
  67         return UART_CONSOLE_INVALID_INDEX;
  68 }
  69
  70 void uart_common_init(const struct device *device, uintptr_t baseaddr)
  71 {
  72 #if defined(__SIMPLE_DEVICE__)
  73         pci_devfn_t dev = PCI_BDF(device);
  74 #else
  75         const struct device *dev = device;
  76 #endif
  77
  78         /* Set UART base address */
  79         pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
  80
  81         /* Enable memory access and bus master */
  82         pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);
  83
  84         uart_lpss_init(device, baseaddr);
  85 }
  86
  87 const struct device *uart_get_device(void)
  88 {
  89         /*
  90          * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE
  91          * config option is not selected.
  92          * By default return NULL in this case to avoid compilation errors.
  93          */
  94         if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
  95                 return NULL;
  96
  97         int console_index = uart_get_valid_index();
  98
  99         if (console_index != UART_CONSOLE_INVALID_INDEX)
 100                 return soc_uart_console_to_device(CONFIG_UART_FOR_CONSOLE);
 101         else
 102                 return NULL;
 103 }
 104
 105 bool uart_is_controller_initialized(void)
 106 {
 107         uintptr_t base;
 108         const struct device *dev_uart = uart_get_device();
 109
 110         if (!dev_uart)
 111                 return false;
 112
 113 #if defined(__SIMPLE_DEVICE__)
 114         pci_devfn_t dev = PCI_BDF(dev_uart);
 115 #else
 116         const struct device *dev = dev_uart;
 117 #endif
 118
 119         base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
 120         if (!base)
 121                 return false;
 122
 123         if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE)
 124             != UART_PCI_ENABLE)
 125                 return false;
 126
 127         return !lpss_is_controller_in_reset(base);
 128 }
 129
 130 static void uart_configure_gpio_pads(void)
 131 {
 132         int index = uart_get_valid_index();
 133
 134         if (index != UART_CONSOLE_INVALID_INDEX)
 135                 gpio_configure_pads(uart_gpio_pads[index].gpios,
 136                                 MAX_GPIO_PAD_PER_UART);
 137 }
 138
 139 void uart_bootblock_init(void)
 140 {
 141         const struct device *dev_uart;
 142
 143         dev_uart = uart_get_device();
 144
 145         if (!dev_uart)
 146                 return;
 147
 148         /* Program UART BAR0, command, reset and clock register */
 149         uart_common_init(dev_uart, CONFIG_CONSOLE_UART_BASE_ADDRESS);
 150
 151         /* Configure the 2 pads per UART. */
 152         uart_configure_gpio_pads();
 153 }
 154
 155 #if ENV_RAMSTAGE
 156
 157 static void uart_read_resources(struct device *dev)
 158 {
 159         pci_dev_read_resources(dev);
 160
 161         /* Set the configured UART base address for the debug port */
 162         if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) &&
 163             uart_is_debug_controller(dev)) {
 164                 struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 165                 /* Need to set the base and size for the resource allocator. */
 166                 res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
 167                 res->size = 0x1000;
 168                 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
 169                                 IORESOURCE_FIXED;
 170         }
 171 }
 172
 173 /*
 174  * Check if UART debug port controller needs to be initialized on resume.
 175  *
 176  * Returns:
 177  * true = when SoC wants debug port initialization on resume
 178  * false = otherwise
 179  */
 180 static bool pch_uart_init_debug_controller_on_resume(void)
 181 {
 182         global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 183
 184         if (gnvs)
 185                 return !!gnvs->uior;
 186
 187         return false;
 188 }
 189
 190 bool uart_is_debug_controller(struct device *dev)
 191 {
 192         return dev == uart_get_device();
 193 }
 194
 195 /*
 196  * This is a workaround to enable UART controller for the debug port if:
 197  * 1. CONSOLE_SERIAL is not enabled in coreboot, and
 198  * 2. This boot is S3 resume, and
 199  * 3. SoC wants to initialize debug UART controller.
 200  *
 201  * This workaround is required because Linux kernel hangs on resume if console
 202  * is not enabled in coreboot, but it is enabled in kernel and not suspended.
 203  */
 204 static bool uart_controller_needs_init(struct device *dev)
 205 {
 206         /*
 207          * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing
 208          * controller here.
 209          */
 210         if (CONFIG(CONSOLE_SERIAL))
 211                 return false;
 212
 213         /* If this device does not correspond to debug port, then skip. */
 214         if (!uart_is_debug_controller(dev))
 215                 return false;
 216
 217         /* Initialize UART controller only on S3 resume. */
 218         if (!acpi_is_wakeup_s3())
 219                 return false;
 220
 221         /*
 222          * check if SOC wants to initialize UART on resume
 223          */
 224         return pch_uart_init_debug_controller_on_resume();
 225 }
 226
 227 static void uart_common_enable_resources(struct device *dev)
 228 {
 229         pci_dev_enable_resources(dev);
 230
 231         if (uart_controller_needs_init(dev)) {
 232                 uintptr_t base;
 233
 234                 base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
 235                 if (base)
 236                         uart_lpss_init(dev, base);
 237         }
 238 }
 239
 240 static struct device_operations device_ops = {
 241         .read_resources         = uart_read_resources,
 242         .set_resources          = pci_dev_set_resources,
 243         .enable_resources       = uart_common_enable_resources,
 244         .ops_pci                = &pci_dev_ops_pci,
 245 };
 246
 247 static const unsigned short pci_device_ids[] = {
 248         PCI_DEVICE_ID_INTEL_SPT_UART0,
 249         PCI_DEVICE_ID_INTEL_SPT_UART1,
 250         PCI_DEVICE_ID_INTEL_SPT_UART2,
 251         PCI_DEVICE_ID_INTEL_SPT_H_UART0,
 252         PCI_DEVICE_ID_INTEL_SPT_H_UART1,
 253         PCI_DEVICE_ID_INTEL_SPT_H_UART2,
 254         PCI_DEVICE_ID_INTEL_KBP_H_UART0,
 255         PCI_DEVICE_ID_INTEL_KBP_H_UART1,
 256         PCI_DEVICE_ID_INTEL_KBP_H_UART2,
 257         PCI_DEVICE_ID_INTEL_APL_UART0,
 258         PCI_DEVICE_ID_INTEL_APL_UART1,
 259         PCI_DEVICE_ID_INTEL_APL_UART2,
 260         PCI_DEVICE_ID_INTEL_APL_UART3,
 261         PCI_DEVICE_ID_INTEL_CNL_UART0,
 262         PCI_DEVICE_ID_INTEL_CNL_UART1,
 263         PCI_DEVICE_ID_INTEL_CNL_UART2,
 264         PCI_DEVICE_ID_INTEL_GLK_UART0,
 265         PCI_DEVICE_ID_INTEL_GLK_UART1,
 266         PCI_DEVICE_ID_INTEL_GLK_UART2,
 267         PCI_DEVICE_ID_INTEL_GLK_UART3,
 268         PCI_DEVICE_ID_INTEL_CNP_H_UART0,
 269         PCI_DEVICE_ID_INTEL_CNP_H_UART1,
 270         PCI_DEVICE_ID_INTEL_CNP_H_UART2,
 271         PCI_DEVICE_ID_INTEL_ICP_UART0,
 272         PCI_DEVICE_ID_INTEL_ICP_UART1,
 273         PCI_DEVICE_ID_INTEL_ICP_UART2,
 274         PCI_DEVICE_ID_INTEL_CMP_UART0,
 275         PCI_DEVICE_ID_INTEL_CMP_UART1,
 276         PCI_DEVICE_ID_INTEL_CMP_UART2,
 277         PCI_DEVICE_ID_INTEL_CMP_H_UART0,
 278         PCI_DEVICE_ID_INTEL_CMP_H_UART1,
 279         PCI_DEVICE_ID_INTEL_CMP_H_UART2,
 280         PCI_DEVICE_ID_INTEL_TGP_UART0,
 281         PCI_DEVICE_ID_INTEL_TGP_UART1,
 282         PCI_DEVICE_ID_INTEL_TGP_UART2,
 283         PCI_DEVICE_ID_INTEL_MCC_UART0,
 284         PCI_DEVICE_ID_INTEL_MCC_UART1,
 285         PCI_DEVICE_ID_INTEL_MCC_UART2,
 286         PCI_DEVICE_ID_INTEL_JSP_UART0,
 287         PCI_DEVICE_ID_INTEL_JSP_UART1,
 288         PCI_DEVICE_ID_INTEL_JSP_UART2,
 289         0,
 290 };
 291
 292 static const struct pci_driver pch_uart __pci_driver = {
 293         .ops            = &device_ops,
 294         .vendor         = PCI_VENDOR_ID_INTEL,
 295         .devices        = pci_device_ids,
 296 };
 297 #endif /* ENV_RAMSTAGE */