src/soc/intel/common/block/systemagent/memmap.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/romstage.h>
  16 #include <cbmem.h>
  17 #include <console/console.h>
  18 #include <cpu/x86/mtrr.h>
  19 #include <cpu/x86/smm.h>
  20 #include <intelblocks/systemagent.h>
  21
  22 /*
  23  * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs):
  24  *
  25  * +---------------------------+ TOUUD
  26  * |                           |
  27  * +---------------------------+ TOM (if mem > 4GB)
  28  * | CSME UMA (if mem > 4 GiB) |
  29  * +---------------------------+ TOUUD
  30  * |                           |
  31  * +---------------------------+ 4GiB
  32  * | PCI Address Space         |
  33  * +---------------------------+ TOM (if mem < 4GB)
  34  * | CSME UMA (if mem < 4 GiB) |
  35  * +---------------------------+ TOLUD (also maps into MC address space)
  36  * | iGD / DSM                 |
  37  * +---------------------------+ BDSM
  38  * | GTT / GSM                 |
  39  * +---------------------------+ TOLM
  40  * | TSEG                      |
  41  * +---------------------------+ TSEGMB
  42  * | DMA Protected Region      |
  43  * +---------------------------+ DPR
  44  * | PRM (C6DRAM/SGX)          |
  45  * +---------------------------+ PRMRR
  46  * | Probeless Trace           |
  47  * +---------------------------+ ME Stolen
  48  * | PTT                       |
  49  * +---------------------------+ TOLUM / top_of_ram / cbmem_top
  50  * | CBMEM Root                |
  51  * +---------------------------+
  52  * | FSP Reserved Memory       |
  53  * +---------------------------+
  54  * | various CBMEM entries     |
  55  * +---------------------------+ top_of_stack (8 byte aligned)
  56  * | stack (CBMEM entry)       |
  57  * +---------------------------+ FSP TOLUM
  58  * |                           |
  59  * +---------------------------+ 0
  60  */
  61
  62 void smm_region(uintptr_t *start, size_t *size)
  63 {
  64         *start = sa_get_tseg_base();
  65         *size = sa_get_tseg_size();
  66 }
  67
  68 void fill_postcar_frame(struct postcar_frame *pcf)
  69 {
  70         uintptr_t top_of_ram;
  71
  72         /*
  73          * We need to make sure ramstage will be run cached. At this
  74          * point exact location of ramstage in cbmem is not known.
  75          * Instruct postcar to cache 16 megs under cbmem top which is
  76          * a safe bet to cover ramstage.
  77          */
  78         top_of_ram = (uintptr_t) cbmem_top();
  79         printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
  80         top_of_ram -= 16*MiB;
  81         postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
  82
  83         /* Cache the TSEG region */
  84         postcar_enable_tseg_cache(pcf);
  85 }