src/soc/intel/common/block/include/intelblocks/systemagent.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef SOC_INTEL_COMMON_BLOCK_SA_H
  16 #define SOC_INTEL_COMMON_BLOCK_SA_H
  17
  18 #include <device/device.h>
  19 #include <soc/iomap.h>
  20 #include <soc/nvs.h>
  21 #include <stddef.h>
  22
  23 /* Device 0:0.0 PCI configuration space */
  24 #define MCHBAR          0x48
  25 #define PCIEXBAR                0x60
  26 #define TOUUD   0xa8 /* Top of Upper Usable DRAM */
  27 #define BDSM    0xb0 /* Base Data Stolen Memory */
  28 #define BGSM    0xb4 /* Base GTT Stolen Memory */
  29 #define TSEG    0xb8 /* TSEG base */
  30 #define TOLUD   0xbc /* Top of Low Used Memory */
  31
  32 /* MCHBAR */
  33 #define MCHBAR8(x)      (*(volatile u8 *)(MCH_BASE_ADDRESS + x))
  34 #define MCHBAR16(x)     (*(volatile u16 *)(MCH_BASE_ADDRESS + x))
  35 #define MCHBAR32(x)     (*(volatile u32 *)(MCH_BASE_ADDRESS + x))
  36 #define MCHBAR64(x)     (*(volatile u64 *)(MCH_BASE_ADDRESS + x))
  37
  38 /* Perform System Agent Initialization during Bootblock phase */
  39 void bootblock_systemagent_early_init(void);
  40
  41 /*
  42  * Fixed MMIO range
  43  *   INDEX = Either PCI configuration space registers or MMIO offsets
  44  *   mapped from REG.
  45  *   BASE = 64 bit Address.
  46  *   SIZE = base length
  47  *   DESCRIPTION = Name of the register/offset.
  48  */
  49 struct sa_mmio_descriptor {
  50         unsigned int index;
  51         uint64_t base;
  52         size_t size;
  53         const char *description;
  54 };
  55
  56 /* API to set Fixed MMIO address into PCI configuration space */
  57 void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,
  58                 size_t count);
  59 /* API to set Fixed MMIO address into MCH base address */
  60 void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources,
  61                 size_t count);
  62 /*
  63  * API to program fixed mmio resource range based on SoC input
  64  * struct sa_mmio_descriptor
  65  */
  66 void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt,
  67         const struct sa_mmio_descriptor *sa_fixed_resources, size_t count);
  68 /*
  69  * API to set BIOS Reset CPL through MCHBAR
  70  * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h
  71  */
  72 void enable_bios_reset_cpl(void);
  73 /* API to enable PAM registers */
  74 void enable_pam_region(void);
  75 /* API to enable Power Aware Interrupt Routing through MCHBAR */
  76 void enable_power_aware_intr(void);
  77 /* API to get TOLUD base address */
  78 uintptr_t sa_get_tolud_base(void);
  79 /* API to get GSM base address */
  80 uintptr_t sa_get_gsm_base(void);
  81 /* API to get TSEG base address */
  82 uintptr_t sa_get_tseg_base(void);
  83 /* API to get TSEG size */
  84 size_t sa_get_tseg_size(void);
  85 /* Fill MMIO resource above 4GB into GNVS */
  86 void sa_fill_gnvs(global_nvs_t *gnvs);
  87 /*
  88  * SoC overrides
  89  *
  90  * All new SoC must implement below functionality for ramstage.
  91  */
  92
  93 /* Perform System Agent Initialization during Ramstage phase */
  94 void soc_systemagent_init(struct device *dev);
  95 /*
  96  * SoC call to provide all known fixed memory ranges for Device 0:0.0.
  97  * SoC function should provide fixed resource ranges in form of
  98  * struct sa_mmio_descriptor along with resource count.
  99  */
 100 void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt);
 101
 102 /* SoC specific APIs to get UNCORE PRMRR base and mask values
 103  * returns 0, if able to get base and mask values; otherwise returns -1 */
 104 int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask);
 105 #endif  /* SOC_INTEL_COMMON_BLOCK_SA_H */