src/soc/intel/cannonlake/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/acpi.h>
  16 #include <arch/acpigen.h>
  17 #include <arch/smp/mpspec.h>
  18 #include <cbmem.h>
  19 #include <console/console.h>
  20 #include <device/mmio.h>
  21 #include <device/pci_ops.h>
  22 #include <ec/google/chromeec/ec.h>
  23 #include <intelblocks/cpulib.h>
  24 #include <intelblocks/pmclib.h>
  25 #include <intelblocks/acpi.h>
  26 #include <intelblocks/p2sb.h>
  27 #include <soc/cpu.h>
  28 #include <soc/iomap.h>
  29 #include <soc/nvs.h>
  30 #include <soc/pci_devs.h>
  31 #include <soc/pm.h>
  32 #include <soc/systemagent.h>
  33 #include <string.h>
  34 #include <vendorcode/google/chromeos/gnvs.h>
  35 #include <wrdd.h>
  36
  37 #include "chip.h"
  38
  39 /*
  40  * List of supported C-states in this processor.
  41  */
  42 enum {
  43         C_STATE_C0,             /* 0 */
  44         C_STATE_C1,             /* 1 */
  45         C_STATE_C1E,            /* 2 */
  46         C_STATE_C6_SHORT_LAT,   /* 3 */
  47         C_STATE_C6_LONG_LAT,    /* 4 */
  48         C_STATE_C7_SHORT_LAT,   /* 5 */
  49         C_STATE_C7_LONG_LAT,    /* 6 */
  50         C_STATE_C7S_SHORT_LAT,  /* 7 */
  51         C_STATE_C7S_LONG_LAT,   /* 8 */
  52         C_STATE_C8,             /* 9 */
  53         C_STATE_C9,             /* 10 */
  54         C_STATE_C10,            /* 11 */
  55         NUM_C_STATES
  56 };
  57
  58 #define MWAIT_RES(state, sub_state)                             \
  59         {                                                       \
  60                 .addrl = (((state) << 4) | (sub_state)),        \
  61                 .space_id = ACPI_ADDRESS_SPACE_FIXED,           \
  62                 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,        \
  63                 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,        \
  64                 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,     \
  65         }
  66
  67 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  68         [C_STATE_C0] = {},
  69         [C_STATE_C1] = {
  70                 .latency = 0,
  71                 .power = C1_POWER,
  72                 .resource = MWAIT_RES(0, 0),
  73         },
  74         [C_STATE_C1E] = {
  75                 .latency = 0,
  76                 .power = C1_POWER,
  77                 .resource = MWAIT_RES(0, 1),
  78         },
  79         [C_STATE_C6_SHORT_LAT] = {
  80                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
  81                 .power = C6_POWER,
  82                 .resource = MWAIT_RES(2, 0),
  83         },
  84         [C_STATE_C6_LONG_LAT] = {
  85                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
  86                 .power = C6_POWER,
  87                 .resource = MWAIT_RES(2, 1),
  88         },
  89         [C_STATE_C7_SHORT_LAT] = {
  90                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
  91                 .power = C7_POWER,
  92                 .resource = MWAIT_RES(3, 0),
  93         },
  94         [C_STATE_C7_LONG_LAT] = {
  95                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
  96                 .power = C7_POWER,
  97                 .resource = MWAIT_RES(3, 1),
  98         },
  99         [C_STATE_C7S_SHORT_LAT] = {
 100                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
 101                 .power = C7_POWER,
 102                 .resource = MWAIT_RES(3, 2),
 103         },
 104         [C_STATE_C7S_LONG_LAT] = {
 105                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
 106                 .power = C7_POWER,
 107                 .resource = MWAIT_RES(3, 3),
 108         },
 109         [C_STATE_C8] = {
 110                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
 111                 .power = C8_POWER,
 112                 .resource = MWAIT_RES(4, 0),
 113         },
 114         [C_STATE_C9] = {
 115                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
 116                 .power = C9_POWER,
 117                 .resource = MWAIT_RES(5, 0),
 118         },
 119         [C_STATE_C10] = {
 120                 .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
 121                 .power = C10_POWER,
 122                 .resource = MWAIT_RES(6, 0),
 123         },
 124 };
 125
 126 static int cstate_set_non_s0ix[] = {
 127         C_STATE_C1E,
 128         C_STATE_C6_LONG_LAT,
 129         C_STATE_C7S_LONG_LAT
 130 };
 131
 132 static int cstate_set_s0ix[] = {
 133         C_STATE_C1E,
 134         C_STATE_C7S_LONG_LAT,
 135         C_STATE_C10
 136 };
 137
 138 acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 139 {
 140         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 141                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 142         int *set;
 143         int i;
 144
 145         config_t *config = config_of_soc();
 146
 147         int is_s0ix_enable = config->s0ix_enable;
 148
 149         if (is_s0ix_enable) {
 150                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 151                 set = cstate_set_s0ix;
 152         } else {
 153                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 154                 set = cstate_set_non_s0ix;
 155         }
 156
 157         for (i = 0; i < *entries; i++) {
 158                 memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
 159                 map[i].ctype = i + 1;
 160         }
 161         return map;
 162 }
 163
 164 void soc_power_states_generation(int core_id, int cores_per_package)
 165 {
 166         config_t *config = config_of_soc();
 167
 168         /* Generate P-state tables */
 169         if (config->eist_enable)
 170                 generate_p_state_entries(core_id, cores_per_package);
 171 }
 172
 173 void soc_fill_fadt(acpi_fadt_t *fadt)
 174 {
 175         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 176         const struct soc_intel_cannonlake_config *config;
 177         config = config_of_soc();
 178
 179         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 180         fadt->pm_tmr_len = 4;
 181         fadt->x_pm_tmr_blk.space_id = 1;
 182         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 183         fadt->x_pm_tmr_blk.bit_offset = 0;
 184         fadt->x_pm_tmr_blk.access_size = 0;
 185         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 186         fadt->x_pm_tmr_blk.addrh = 0x0;
 187
 188         if (config->s0ix_enable)
 189                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 190 }
 191 uint32_t soc_read_sci_irq_select(void)
 192 {
 193         uintptr_t pmc_bar = soc_read_pmc_base();
 194         return read32((void *)pmc_bar + IRQ_REG);
 195 }
 196
 197 void acpi_create_gnvs(struct global_nvs_t *gnvs)
 198 {
 199         const struct soc_intel_cannonlake_config *config;
 200         config = config_of_soc();
 201
 202         /* Set unknown wake source */
 203         gnvs->pm1i = -1;
 204
 205         /* CPU core count */
 206         gnvs->pcnt = dev_count_cpu();
 207
 208         /* Update the mem console pointer. */
 209         if (CONFIG(CONSOLE_CBMEM))
 210                 gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
 211
 212         if (CONFIG(CHROMEOS)) {
 213                 /* Initialize Verified Boot data */
 214                 chromeos_init_chromeos_acpi(&(gnvs->chromeos));
 215                 if (CONFIG(EC_GOOGLE_CHROMEEC)) {
 216                         gnvs->chromeos.vbt2 = google_ec_running_ro() ?
 217                                 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
 218                 } else
 219                         gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
 220         }
 221
 222         /* Enable DPTF based on mainboard configuration */
 223         gnvs->dpte = config->dptf_enable;
 224
 225         /* Fill in the Wifi Region id */
 226         gnvs->cid1 = wifi_regulatory_domain();
 227
 228         /* Set USB2/USB3 wake enable bitmaps. */
 229         gnvs->u2we = config->usb2_wake_enable_bitmap;
 230         gnvs->u3we = config->usb3_wake_enable_bitmap;
 231
 232         /* Fill in Above 4GB MMIO resource */
 233         sa_fill_gnvs(gnvs);
 234 }
 235
 236 uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
 237                             const struct chipset_power_state *ps)
 238 {
 239         /*
 240          * WAK_STS bit is set when the system is in one of the sleep states
 241          * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
 242          * this bit, the PMC will transition the system to the ON state and
 243          * can only be set by hardware and can only be cleared by writing a one
 244          * to this bit position.
 245          */
 246
 247         generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
 248         return generic_pm1_en;
 249 }
 250
 251 int soc_madt_sci_irq_polarity(int sci)
 252 {
 253         return MP_IRQ_POLARITY_HIGH;
 254 }
 255
 256 static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
 257 {
 258         /* op (gpio_num) */
 259         acpigen_emit_namestring(op);
 260         acpigen_write_integer(gpio_num);
 261         return 0;
 262 }
 263
 264 static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
 265 {
 266         /* Store (op (gpio_num), Local0) */
 267         acpigen_write_store();
 268         acpigen_soc_gpio_op(op, gpio_num);
 269         acpigen_emit_byte(LOCAL0_OP);
 270         return 0;
 271 }
 272
 273 int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
 274 {
 275         return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num);
 276 }
 277
 278 int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
 279 {
 280         return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num);
 281 }
 282
 283 int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
 284 {
 285         return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num);
 286 }
 287
 288 int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 289 {
 290         return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num);
 291 }
 292
 293 static unsigned long soc_fill_dmar(unsigned long current)
 294 {
 295         struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 296         uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 297         bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 298
 299         if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
 300                 unsigned long tmp = current;
 301
 302                 current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 303                 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 304
 305                 acpi_dmar_drhd_fixup(tmp, current);
 306         }
 307
 308         struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
 309         uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 310         bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 311
 312         if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
 313                 unsigned long tmp = current;
 314
 315                 current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
 316                 current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
 317
 318                 acpi_dmar_drhd_fixup(tmp, current);
 319         }
 320
 321         uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
 322         bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
 323
 324         if (vtvc0bar && vtvc0en) {
 325                 const unsigned long tmp = current;
 326
 327                 current += acpi_create_dmar_drhd(current,
 328                                 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
 329                 current += acpi_create_dmar_ds_ioapic(current,
 330                                 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
 331                                 V_P2SB_CFG_IBDF_FUNC);
 332                 current += acpi_create_dmar_ds_msi_hpet(current,
 333                                 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
 334                                 V_P2SB_CFG_HBDF_FUNC);
 335
 336                 acpi_dmar_drhd_fixup(tmp, current);
 337         }
 338
 339         /* Add RMRR entry */
 340         const unsigned long tmp = current;
 341         current += acpi_create_dmar_rmrr(current, 0,
 342                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 343         current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 344         acpi_dmar_rmrr_fixup(tmp, current);
 345
 346         return current;
 347 }
 348
 349 unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
 350                                    struct acpi_rsdp *rsdp)
 351 {
 352         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 353
 354         /* Create DMAR table only if we have VT-d capability
 355          * and FSP does not override its feature.
 356          */
 357         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 358             !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
 359                 return current;
 360
 361         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 362         acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
 363
 364         current += dmar->header.length;
 365         current = acpi_align_current(current);
 366         acpi_add_table(rsdp, dmar);
 367
 368         return current;
 369 }