src/soc/intel/broadwell/pcie.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <console/console.h>
  16 #include <device/device.h>
  17 #include <device/pci.h>
  18 #include <device/pciexp.h>
  19 #include <device/pci_def.h>
  20 #include <device/pci_ids.h>
  21 #include <device/pci_ops.h>
  22 #include <soc/gpio.h>
  23 #include <soc/lpc.h>
  24 #include <soc/iobp.h>
  25 #include <soc/pch.h>
  26 #include <soc/pci_devs.h>
  27 #include <soc/rcba.h>
  28 #include <soc/intel/broadwell/chip.h>
  29 #include <soc/cpu.h>
  30 #include <delay.h>
  31
  32 /* Low Power variant has 6 root ports. */
  33 #define NUM_ROOT_PORTS 6
  34
  35 struct root_port_config {
  36         /* RPFN is a write-once register so keep a copy until it is written */
  37         u32 orig_rpfn;
  38         u32 new_rpfn;
  39         u32 pin_ownership;
  40         u32 strpfusecfg1;
  41         u32 strpfusecfg2;
  42         u32 strpfusecfg3;
  43         u32 b0d28f0_32c;
  44         u32 b0d28f4_32c;
  45         u32 b0d28f5_32c;
  46         int coalesce;
  47         int gbe_port;
  48         int num_ports;
  49         struct device *ports[NUM_ROOT_PORTS];
  50 };
  51
  52 static struct root_port_config rpc;
  53
  54 static inline int root_port_is_first(struct device *dev)
  55 {
  56         return PCI_FUNC(dev->path.pci.devfn) == 0;
  57 }
  58
  59 static inline int root_port_is_last(struct device *dev)
  60 {
  61         return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
  62 }
  63
  64 /* Root ports are numbered 1..N in the documentation. */
  65 static inline int root_port_number(struct device *dev)
  66 {
  67         return PCI_FUNC(dev->path.pci.devfn) + 1;
  68 }
  69
  70 static void root_port_config_update_gbe_port(void)
  71 {
  72         /* Is the Gbe Port enabled? */
  73         if (!((rpc.strpfusecfg1 >> 19) & 1))
  74                 return;
  75
  76         switch ((rpc.strpfusecfg1 >> 16) & 0x7) {
  77         case 0:
  78                 rpc.gbe_port = 3;
  79                 break;
  80         case 1:
  81                 rpc.gbe_port = 4;
  82                 break;
  83         case 2:
  84         case 3:
  85         case 4:
  86         case 5:
  87                 /* Lanes 0-4 of Root Port 5. */
  88                 rpc.gbe_port = 5;
  89                 break;
  90         default:
  91                 printk(BIOS_DEBUG, "Invalid GbE Port Selection.\n");
  92         }
  93 }
  94
  95 static void pcie_iosf_port_grant_count(struct device *dev)
  96 {
  97         u8 update_val;
  98         u32 rpcd = (pci_read_config32(dev, 0xfc) >> 14) & 0x3;
  99
 100         switch (rpcd) {
 101         case 1:
 102         case 3:
 103                 update_val = 0x02;
 104                 break;
 105         case 2:
 106                 update_val = 0x22;
 107                 break;
 108         default:
 109                 update_val = 0x00;
 110                 break;
 111         }
 112
 113         RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val;
 114 }
 115
 116 static void root_port_init_config(struct device *dev)
 117 {
 118         int rp;
 119         u32 data = 0;
 120         u8 resp, id;
 121
 122         if (root_port_is_first(dev)) {
 123                 rpc.orig_rpfn = RCBA32(RPFN);
 124                 rpc.new_rpfn = rpc.orig_rpfn;
 125                 rpc.num_ports = NUM_ROOT_PORTS;
 126                 rpc.gbe_port = -1;
 127                 /* RP0 f5[3:0] = 0101b*/
 128                 pci_update_config8(dev, 0xf5, ~0xa, 0x5);
 129
 130                 pcie_iosf_port_grant_count(dev);
 131
 132                 rpc.pin_ownership = pci_read_config32(dev, 0x410);
 133                 root_port_config_update_gbe_port();
 134
 135                 pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
 136                 config_t *config = config_of(dev);
 137                 rpc.coalesce = config->pcie_port_coalesce;
 138         }
 139
 140         rp = root_port_number(dev);
 141         if (rp > rpc.num_ports) {
 142                 printk(BIOS_ERR, "Found Root Port %d, expecting %d\n",
 143                        rp, rpc.num_ports);
 144                 return;
 145         }
 146
 147         /* Read the fuse configuration and pin ownership. */
 148         switch (rp) {
 149         case 1:
 150                 rpc.strpfusecfg1 = pci_read_config32(dev, 0xfc);
 151                 rpc.b0d28f0_32c = pci_read_config32(dev, 0x32c);
 152                 break;
 153         case 5:
 154                 rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc);
 155                 rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c);
 156                 break;
 157         case 6:
 158                 rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c);
 159                 rpc.strpfusecfg3 = pci_read_config32(dev, 0xfc);
 160                 break;
 161         default:
 162                 break;
 163         }
 164
 165         pci_update_config32(dev, 0x418, 0, 0x02000430);
 166
 167         if (root_port_is_first(dev)) {
 168                 /*
 169                  * set RP0 PCICFG E2h[5:4] = 11b and E1h[6] = 1
 170                  * before configuring ASPM
 171                  */
 172                 id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07);
 173                 pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp);
 174                 data |= ((0x30 << 16) | (0x40 << 8));
 175                 pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp);
 176         }
 177
 178         /* Cache pci device. */
 179         rpc.ports[rp - 1] = dev;
 180 }
 181
 182 /* Update devicetree with new Root Port function number assignment */
 183 static void pch_pcie_device_set_func(int index, int pci_func)
 184 {
 185         struct device *dev;
 186         unsigned int new_devfn;
 187
 188         dev = rpc.ports[index];
 189
 190         /* Set the new PCI function field for this Root Port. */
 191         rpc.new_rpfn &= ~RPFN_FNMASK(index);
 192         rpc.new_rpfn |= RPFN_FNSET(index, pci_func);
 193
 194         /* Determine the new devfn for this port */
 195         new_devfn = PCI_DEVFN(PCH_DEV_SLOT_PCIE, pci_func);
 196
 197         if (dev->path.pci.devfn != new_devfn) {
 198                 printk(BIOS_DEBUG,
 199                        "PCH: PCIe map %02x.%1x -> %02x.%1x\n",
 200                        PCI_SLOT(dev->path.pci.devfn),
 201                        PCI_FUNC(dev->path.pci.devfn),
 202                        PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
 203
 204                 dev->path.pci.devfn = new_devfn;
 205         }
 206 }
 207
 208 static void pcie_enable_clock_gating(void)
 209 {
 210         int i;
 211         int enabled_ports = 0;
 212         int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
 213
 214         for (i = 0; i < rpc.num_ports; i++) {
 215                 struct device *dev;
 216                 int rp;
 217
 218                 dev = rpc.ports[i];
 219                 rp = root_port_number(dev);
 220
 221                 if (!dev->enabled) {
 222                         /* Configure shared resource clock gating. */
 223                         if (rp == 1 || rp == 5 || rp == 6)
 224                                 pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
 225
 226                         pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
 227                         pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));
 228
 229                         /* Per-Port CLKREQ# handling. */
 230                         if (gpio_is_native(18 + rp - 1))
 231                                 pci_update_config32(dev, 0x420, ~0, (3 << 29));
 232
 233                         /* Enable static clock gating. */
 234                         if (rp == 1 && !rpc.ports[1]->enabled &&
 235                             !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) {
 236                                 pci_update_config8(dev, 0xe2, ~1, 1);
 237                                 pci_update_config8(dev, 0xe1, 0x7f, 0x80);
 238                         } else if (rp == 5 || rp == 6) {
 239                                 pci_update_config8(dev, 0xe2, ~1, 1);
 240                                 pci_update_config8(dev, 0xe1, 0x7f, 0x80);
 241                         }
 242                         continue;
 243                 }
 244
 245                 enabled_ports++;
 246
 247                 /* Enable dynamic clock gating. */
 248                 pci_update_config8(dev, 0xe1, 0xfc, 0x03);
 249                 pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6));
 250                 pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2));
 251
 252                 /* Update PECR1 register. */
 253                 pci_update_config8(dev, 0xe8, ~0, 3);
 254                 if (is_broadwell) {
 255                         pci_update_config32(dev, 0x324, ~((1 << 5) | (1 << 14)),
 256                                         ((1 << 5) | (1 << 14)));
 257                 } else {
 258                         pci_update_config32(dev, 0x324, ~(1 << 5), (1 << 5));
 259                 }
 260                 /* Per-Port CLKREQ# handling. */
 261                 if (gpio_is_native(18 + rp - 1))
 262                         /*
 263                          * In addition to D28Fx PCICFG 420h[30:29] = 11b,
 264                          * set 420h[17] = 0b and 420[0] = 1b for L1 SubState.
 265                          */
 266                         pci_update_config32(dev, 0x420, ~0x20000,
 267                                 (3 << 29) | 1);
 268
 269                 /* Configure shared resource clock gating. */
 270                 if (rp == 1 || rp == 5 || rp == 6)
 271                         pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
 272
 273                 /* CLKREQ# VR Idle Enable */
 274                 RCBA32_OR(0x2b1c, (1 << (16 + i)));
 275         }
 276
 277         if (!enabled_ports)
 278                 pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6));
 279 }
 280
 281 static void root_port_commit_config(void)
 282 {
 283         int i;
 284
 285         /* If the first root port is disabled the coalesce ports. */
 286         if (!rpc.ports[0]->enabled)
 287                 rpc.coalesce = 1;
 288
 289         /* Perform clock gating configuration. */
 290         pcie_enable_clock_gating();
 291
 292         for (i = 0; i < rpc.num_ports; i++) {
 293                 struct device *dev;
 294                 u32 reg32;
 295                 int n = 0;
 296
 297                 dev = rpc.ports[i];
 298
 299                 if (dev == NULL) {
 300                         printk(BIOS_ERR, "Root Port %d device is NULL?\n", i+1);
 301                         continue;
 302                 }
 303
 304                 if (dev->enabled)
 305                         continue;
 306
 307                 printk(BIOS_DEBUG, "%s: Disabling device\n",  dev_path(dev));
 308
 309                 /* 8.2 Configuration of PCI Express Root Ports */
 310                 pci_update_config32(dev, 0x338, ~(1 << 26), 1 << 26);
 311
 312                 do {
 313                         reg32 = pci_read_config32(dev, 0x328);
 314                         n++;
 315                         if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
 316                                 break;
 317                         udelay(100);
 318                 } while (1);
 319
 320                 if (n > 50)
 321                         printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
 322                                 dev_path(dev));
 323
 324                 pci_update_config32(dev, 0x408, ~(1 << 27), 1 << 27);
 325
 326                 /* Disable this device if possible */
 327                 pch_disable_devfn(dev);
 328         }
 329
 330         if (rpc.coalesce) {
 331                 int current_func;
 332
 333                 /* For all Root Ports N enabled ports get assigned the lower
 334                  * PCI function number. The disabled ones get upper PCI
 335                  * function numbers. */
 336                 current_func = 0;
 337                 for (i = 0; i < rpc.num_ports; i++) {
 338                         if (!rpc.ports[i]->enabled)
 339                                 continue;
 340                         pch_pcie_device_set_func(i, current_func);
 341                         current_func++;
 342                 }
 343
 344                 /* Allocate the disabled devices' PCI function number. */
 345                 for (i = 0; i < rpc.num_ports; i++) {
 346                         if (rpc.ports[i]->enabled)
 347                                 continue;
 348                         pch_pcie_device_set_func(i, current_func);
 349                         current_func++;
 350                 }
 351         }
 352
 353         printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
 354                rpc.orig_rpfn, rpc.new_rpfn);
 355         RCBA32(RPFN) = rpc.new_rpfn;
 356 }
 357
 358 static void root_port_mark_disable(struct device *dev)
 359 {
 360         /* Mark device as disabled. */
 361         dev->enabled = 0;
 362         /* Mark device to be hidden. */
 363         rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
 364 }
 365
 366 static void root_port_check_disable(struct device *dev)
 367 {
 368         int rp;
 369
 370         /* Device already disabled. */
 371         if (!dev->enabled) {
 372                 root_port_mark_disable(dev);
 373                 return;
 374         }
 375
 376         rp = root_port_number(dev);
 377
 378         /* Is the GbE port mapped to this Root Port? */
 379         if (rp == rpc.gbe_port) {
 380                 root_port_mark_disable(dev);
 381                 return;
 382         }
 383
 384         /* Check Root Port Configuration. */
 385         switch (rp) {
 386         case 2:
 387                 /* Root Port 2 is disabled for all lane configurations
 388                  * but config 00b (4x1 links). */
 389                 if ((rpc.strpfusecfg1 >> 14) & 0x3) {
 390                         root_port_mark_disable(dev);
 391                         return;
 392                 }
 393                 break;
 394         case 3:
 395                 /* Root Port 3 is disabled in config 11b (1x4 links). */
 396                 if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
 397                         root_port_mark_disable(dev);
 398                         return;
 399                 }
 400                 break;
 401         case 4:
 402                 /* Root Port 4 is disabled in configs 11b (1x4 links)
 403                  * and 10b (2x2 links). */
 404                 if ((rpc.strpfusecfg1 >> 14) & 0x2) {
 405                         root_port_mark_disable(dev);
 406                         return;
 407                 }
 408                 break;
 409         }
 410
 411         /* Check Pin Ownership. */
 412         switch (rp) {
 413         case 1:
 414                 /* Bit 0 is Root Port 1 ownership. */
 415                 if ((rpc.pin_ownership & 0x1) == 0) {
 416                         root_port_mark_disable(dev);
 417                         return;
 418                 }
 419                 break;
 420         case 2:
 421                 /* Bit 2 is Root Port 2 ownership. */
 422                 if ((rpc.pin_ownership & 0x4) == 0) {
 423                         root_port_mark_disable(dev);
 424                         return;
 425                 }
 426                 break;
 427         case 6:
 428                 /* Bits 7:4 are Root Port 6 pin-lane ownership. */
 429                 if ((rpc.pin_ownership & 0xf0) == 0) {
 430                         root_port_mark_disable(dev);
 431                         return;
 432                 }
 433                 break;
 434         }
 435 }
 436
 437 static void pcie_add_0x0202000_iobp(u32 reg)
 438 {
 439         u32 reg32;
 440
 441         reg32 = pch_iobp_read(reg);
 442         reg32 += (0x2 << 16) | (0x2 << 8);
 443         pch_iobp_write(reg, reg32);
 444 }
 445
 446 static void pch_pcie_early(struct device *dev)
 447 {
 448         config_t *config = config_of(dev);
 449         int do_aspm = 0;
 450         int rp = root_port_number(dev);
 451
 452         switch (rp) {
 453         case 1:
 454         case 2:
 455         case 3:
 456         case 4:
 457                 /*
 458                  * Bits 31:28 of b0d28f0 0x32c register correspond to
 459                  * Root Ports 4:1.
 460                  */
 461                 do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
 462                 break;
 463         case 5:
 464                 /*
 465                  * Bit 28 of b0d28f4 0x32c register correspond to
 466                  * Root Ports 4:1.
 467                  */
 468                 do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
 469                 break;
 470         case 6:
 471                 /*
 472                  * Bit 28 of b0d28f5 0x32c register correspond to
 473                  * Root Ports 4:1.
 474                  */
 475                 do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
 476                 break;
 477         }
 478
 479         /* Allow ASPM to be forced on in devicetree */
 480         if ((config->pcie_port_force_aspm & (1 << (rp - 1))))
 481                 do_aspm = 1;
 482
 483         printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",
 484                rp, do_aspm ? "en" : "dis");
 485
 486         if (do_aspm) {
 487                 /* Set ASPM bits in MPC2 register. */
 488                 pci_update_config32(dev, 0xd4, ~(0x3 << 2),
 489                         (1 << 4) | (0x2 << 2));
 490
 491                 /* Set unique clock exit latency in MPC register. */
 492                 pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
 493
 494                 switch (rp) {
 495                 case 1:
 496                         pcie_add_0x0202000_iobp(0xe9002440);
 497                         break;
 498                 case 2:
 499                         pcie_add_0x0202000_iobp(0xe9002640);
 500                         break;
 501                 case 3:
 502                         pcie_add_0x0202000_iobp(0xe9000840);
 503                         break;
 504                 case 4:
 505                         pcie_add_0x0202000_iobp(0xe9000a40);
 506                         break;
 507                 case 5:
 508                         pcie_add_0x0202000_iobp(0xe9000c40);
 509                         pcie_add_0x0202000_iobp(0xe9000e40);
 510                         pcie_add_0x0202000_iobp(0xe9001040);
 511                         pcie_add_0x0202000_iobp(0xe9001240);
 512                         break;
 513                 case 6:
 514                         /* Update IOBP based on lane ownership. */
 515                         if (rpc.pin_ownership & (1 << 4))
 516                                 pcie_add_0x0202000_iobp(0xea002040);
 517                         if (rpc.pin_ownership & (1 << 5))
 518                                 pcie_add_0x0202000_iobp(0xea002240);
 519                         if (rpc.pin_ownership & (1 << 6))
 520                                 pcie_add_0x0202000_iobp(0xea002440);
 521                         if (rpc.pin_ownership & (1 << 7))
 522                                 pcie_add_0x0202000_iobp(0xea002640);
 523                         break;
 524                 }
 525
 526                 pci_update_config32(dev, 0x338, ~(1 << 26), 0);
 527         }
 528
 529         /* Enable LTR in Root Port. Disable OBFF. */
 530         pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
 531         pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
 532
 533         pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
 534
 535         /* Set L1 exit latency in LCAP register. */
 536         if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
 537                 pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
 538         else
 539                 pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
 540
 541         pci_update_config32(dev, 0x314, 0x0, 0x743a361b);
 542
 543         /* Set Common Clock Exit Latency in MPC register. */
 544         pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
 545
 546         pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74);
 547
 548         /* Set Invalid Receive Range Check Enable in MPC register. */
 549         pci_update_config32(dev, 0xd8, ~0, (1 << 25));
 550
 551         pci_update_config8(dev, 0xf5, 0x0f, 0);
 552
 553         /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
 554         if (CONFIG(PCIEXP_AER))
 555                 pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
 556                         (1 << 29) | 0x10001);
 557         else
 558                 pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
 559                         (1 << 29));
 560
 561         /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
 562         if (CONFIG(PCIEXP_L1_SUB_STATE))
 563                 pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
 564         else
 565                 pci_update_config32(dev, 0x200, ~0xfffff, 0);
 566
 567         pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6),
 568                 (1 << 20) | (3 << 6));
 569         /* Enable Relaxed Order from Root Port. */
 570         pci_update_config32(dev, 0x320, ~(3 << 23), (3 << 23));
 571
 572         if (rp == 1 || rp == 5 || rp == 6)
 573                 pci_update_config8(dev, 0xf7, ~0xc, 0);
 574
 575         /* Set EOI forwarding disable. */
 576         pci_update_config32(dev, 0xd4, ~0, (1 << 1));
 577
 578         /* Read and write back write-once capability registers. */
 579         pci_update_config32(dev, 0x34, ~0, 0);
 580         pci_update_config32(dev, 0x40, ~0, 0);
 581         pci_update_config32(dev, 0x80, ~0, 0);
 582         pci_update_config32(dev, 0x90, ~0, 0);
 583 }
 584
 585 static void pch_pcie_init(struct device *dev)
 586 {
 587         u16 reg16;
 588         u32 reg32;
 589
 590         printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
 591
 592         /* Enable SERR */
 593         reg32 = pci_read_config32(dev, PCI_COMMAND);
 594         reg32 |= PCI_COMMAND_SERR;
 595         pci_write_config32(dev, PCI_COMMAND, reg32);
 596
 597         /* Enable Bus Master */
 598         reg32 = pci_read_config32(dev, PCI_COMMAND);
 599         reg32 |= PCI_COMMAND_MASTER;
 600         pci_write_config32(dev, PCI_COMMAND, reg32);
 601
 602         /* Set Cache Line Size to 0x10 */
 603         pci_write_config8(dev, 0x0c, 0x10);
 604
 605         reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 606         reg16 &= ~PCI_BRIDGE_CTL_PARITY;
 607         reg16 |= PCI_BRIDGE_CTL_NO_ISA;
 608         pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
 609
 610 #ifdef EVEN_MORE_DEBUG
 611         reg32 = pci_read_config32(dev, 0x20);
 612         printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
 613         reg32 = pci_read_config32(dev, 0x24);
 614         printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
 615         reg32 = pci_read_config32(dev, 0x28);
 616         printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
 617         reg32 = pci_read_config32(dev, 0x2c);
 618         printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
 619 #endif
 620
 621         /* Clear errors in status registers */
 622         reg16 = pci_read_config16(dev, 0x06);
 623         pci_write_config16(dev, 0x06, reg16);
 624         reg16 = pci_read_config16(dev, 0x1e);
 625         pci_write_config16(dev, 0x1e, reg16);
 626 }
 627
 628 static void pch_pcie_enable(struct device *dev)
 629 {
 630         /* Add this device to the root port config structure. */
 631         root_port_init_config(dev);
 632
 633         /* Check to see if this Root Port should be disabled. */
 634         root_port_check_disable(dev);
 635
 636         /* Power Management init before enumeration */
 637         if (dev->enabled)
 638                 pch_pcie_early(dev);
 639
 640         /*
 641          * When processing the last PCIe root port we can now
 642          * update the Root Port Function Number and Hide register.
 643          */
 644         if (root_port_is_last(dev))
 645                 root_port_commit_config();
 646 }
 647
 648 static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
 649 {
 650         /* Set max snoop and non-snoop latency for Broadwell */
 651         pci_write_config32(dev, off,
 652                 PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
 653                 PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
 654 }
 655
 656 static struct pci_operations pcie_ops = {
 657         .set_subsystem = pci_dev_set_subsystem,
 658         .set_L1_ss_latency = pcie_set_L1_ss_max_latency,
 659 };
 660
 661 static struct device_operations device_ops = {
 662         .read_resources         = pci_bus_read_resources,
 663         .set_resources          = pci_dev_set_resources,
 664         .enable_resources       = pci_bus_enable_resources,
 665         .init                   = pch_pcie_init,
 666         .enable                 = pch_pcie_enable,
 667         .scan_bus               = pciexp_scan_bridge,
 668         .ops_pci                = &pcie_ops,
 669 };
 670
 671 static const unsigned short pcie_device_ids[] = {
 672         /* Lynxpoint-LP */
 673         0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
 674         /* WildcatPoint */
 675         0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a, 0x2448,
 676         0
 677 };
 678
 679 static const struct pci_driver pch_pcie __pci_driver = {
 680         .ops     = &device_ops,
 681         .vendor  = PCI_VENDOR_ID_INTEL,
 682         .devices = pcie_device_ids,
 683 };