src/soc/intel/broadwell/include/soc/gpio.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef _BROADWELL_GPIO_H_
  16 #define _BROADWELL_GPIO_H_
  17
  18 #include <stdint.h>
  19
  20 #define CROS_GPIO_DEVICE_NAME           "PCH-LP"
  21 #define CROS_GPIO_ACPI_DEVICE_NAME      "INT3437:00"
  22
  23 /* PCH-LP GPIOBASE Registers */
  24 #define GPIO_OWNER(set)         (0x00 + ((set) * 4))
  25 #define GPIO_PIRQ_APIC_EN       0x10
  26 #define GPIO_BLINK              0x18
  27 #define GPIO_SER_BLINK          0x1c
  28 #define GPIO_SER_BLINK_CS       0x20
  29 #define GPIO_SER_BLINK_DATA     0x24
  30 #define GPIO_ROUTE(set)         (0x30 + ((set) * 4))
  31 #define GPIO_ALT_GPI_SMI_STS    0x50
  32 #define GPIO_ALT_GPI_SMI_EN     0x54
  33 #define GPIO_RESET(set)         (0x60 + ((set) * 4))
  34 #define GPIO_GLOBAL_CONFIG      0x7c
  35 #define GPIO_IRQ_IS(set)        (0x80 + ((set) * 4))
  36 #define GPIO_IRQ_IE(set)        (0x90 + ((set) * 4))
  37 #define GPIO_CONFIG0(gpio)      (0x100 + ((gpio) * 8))
  38 #define GPIO_CONFIG1(gpio)      (0x104 + ((gpio) * 8))
  39
  40 #define MAX_GPIO_NUMBER         94 /* zero based */
  41 #define GPIO_LIST_END           0xffffffff
  42
  43 /* conf0 */
  44
  45 #define GPIO_MODE_NATIVE        (0 << 0)
  46 #define GPIO_MODE_GPIO          (1 << 0)
  47
  48 #define GPIO_DIR_OUTPUT         (0 << 2)
  49 #define GPIO_DIR_INPUT          (1 << 2)
  50
  51 #define GPIO_NO_INVERT          (0 << 3)
  52 #define GPIO_INVERT             (1 << 3)
  53
  54 #define GPIO_IRQ_EDGE           (0 << 4)
  55 #define GPIO_IRQ_LEVEL          (1 << 4)
  56
  57 #define GPI_LEVEL               (1 << 30)
  58
  59 #define GPIO_OUT_LOW            0
  60 #define GPIO_OUT_HIGH           1
  61 #define GPO_LEVEL_SHIFT         31
  62 #define GPO_LEVEL_MASK          (1 << GPO_LEVEL_SHIFT)
  63 #define GPO_LEVEL_LOW           (GPIO_OUT_LOW << GPO_LEVEL_SHIFT)
  64 #define GPO_LEVEL_HIGH          (GPIO_OUT_HIGH << GPO_LEVEL_SHIFT)
  65
  66 /* conf1 */
  67
  68 #define GPIO_PULL_NONE          (0 << 0)
  69 #define GPIO_PULL_DOWN          (1 << 0)
  70 #define GPIO_PULL_UP            (2 << 0)
  71
  72 #define GPIO_SENSE_ENABLE       (0 << 2)
  73 #define GPIO_SENSE_DISABLE      (1 << 2)
  74
  75 /* owner */
  76
  77 #define GPIO_OWNER_ACPI         0
  78 #define GPIO_OWNER_GPIO         1
  79
  80 /* route */
  81
  82 #define GPIO_ROUTE_SCI          0
  83 #define GPIO_ROUTE_SMI          1
  84
  85 /* irqen */
  86
  87 #define GPIO_IRQ_DISABLE        0
  88 #define GPIO_IRQ_ENABLE         1
  89
  90 /* blink */
  91
  92 #define GPO_NO_BLINK            0
  93 #define GPO_BLINK               1
  94
  95 /* reset */
  96
  97 #define GPIO_RESET_PWROK        0
  98 #define GPIO_RESET_RSMRST       1
  99
 100 /* pirq route to io-apic */
 101
 102 #define GPIO_PIRQ_APIC_MASK     0
 103 #define GPIO_PIRQ_APIC_ROUTE    1
 104
 105 #define PCH_GPIO_END \
 106         { .conf0 = GPIO_LIST_END }
 107
 108 #define PCH_GPIO_NATIVE \
 109         { .conf0 = GPIO_MODE_NATIVE }
 110
 111 #define PCH_GPIO_UNUSED \
 112         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
 113           .owner = GPIO_OWNER_GPIO, \
 114           .conf1 = GPIO_SENSE_DISABLE }
 115
 116 #define PCH_GPIO_ACPI_SCI \
 117         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
 118           .owner = GPIO_OWNER_ACPI, \
 119           .route = GPIO_ROUTE_SCI }
 120
 121 #define PCH_GPIO_ACPI_SMI \
 122         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
 123           .owner = GPIO_OWNER_ACPI, \
 124           .route = GPIO_ROUTE_SMI }
 125
 126 #define PCH_GPIO_INPUT \
 127         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
 128           .owner = GPIO_OWNER_GPIO }
 129
 130 #define PCH_GPIO_INPUT_INVERT \
 131         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
 132           .owner = GPIO_OWNER_GPIO }
 133
 134 #define PCH_GPIO_IRQ_EDGE \
 135         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \
 136           .owner = GPIO_OWNER_GPIO, \
 137           .irqen = GPIO_IRQ_ENABLE }
 138
 139 #define PCH_GPIO_IRQ_LEVEL \
 140         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \
 141           .owner = GPIO_OWNER_GPIO, \
 142           .irqen = GPIO_IRQ_ENABLE }
 143
 144 #define PCH_GPIO_PIRQ \
 145         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
 146           .owner = GPIO_OWNER_GPIO, \
 147           .pirq  = GPIO_PIRQ_APIC_ROUTE }
 148
 149 #define PCH_GPIO_PIRQ_INVERT \
 150         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
 151           .owner = GPIO_OWNER_GPIO, \
 152           .pirq  = GPIO_PIRQ_APIC_ROUTE }
 153
 154 #define PCH_GPIO_OUT_HIGH \
 155         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \
 156           .owner = GPIO_OWNER_GPIO, \
 157           .conf1 = GPIO_SENSE_DISABLE }
 158
 159 #define PCH_GPIO_OUT_LOW \
 160         { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \
 161           .owner = GPIO_OWNER_GPIO, \
 162           .conf1 = GPIO_SENSE_DISABLE }
 163
 164 struct gpio_config {
 165         u8 gpio;
 166         u32 conf0;
 167         u32 conf1;
 168         u8 owner;
 169         u8 route;
 170         u8 irqen;
 171         u8 reset;
 172         u8 blink;
 173         u8 pirq;
 174 } __packed;
 175
 176 /* Configure GPIOs with mainboard provided settings */
 177 void init_gpios(const struct gpio_config config[]);
 178
 179 /* Get GPIO pin value */
 180 int get_gpio(int gpio_num);
 181
 182 /* Set GPIO pin value */
 183 void set_gpio(int gpio_num, int value);
 184
 185 /* Return non-zero if gpio is set to native function. 0 otherwise. */
 186 int gpio_is_native(int gpio_num);
 187
 188 /*
 189  * Get a number comprised of multiple GPIO values. gpio_num_array points to
 190  * the array of gpio pin numbers to scan, terminated by -1.
 191  */
 192 unsigned int get_gpios(const int *gpio_num_array);
 193
 194 extern const struct gpio_config mainboard_gpio_config[];
 195
 196 #endif