src/soc/intel/braswell/scc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15
  16 #include <cbmem.h>
  17 #include <console/console.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <soc/iosf.h>
  21 #include <soc/nvs.h>
  22 #include <soc/ramstage.h>
  23
  24 void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
  25 {
  26         struct resource *bar;
  27         global_nvs_t *gnvs;
  28
  29         printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n",
  30                         __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);
  31
  32         /* Find ACPI NVS to update BARs */
  33         gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
  34         if (!gnvs) {
  35                 printk(BIOS_ERR, "Unable to locate Global NVS\n");
  36                 return;
  37         }
  38
  39         /* Save BAR0 and BAR1 to ACPI NVS */
  40         bar = find_resource(dev, PCI_BASE_ADDRESS_0);
  41         if (bar)
  42                 gnvs->dev.scc_bar0[nvs_index] = bar->base;
  43         bar = find_resource(dev, PCI_BASE_ADDRESS_2);
  44         if (bar)
  45                 gnvs->dev.scc_bar1[nvs_index] = bar->base;
  46
  47         /* Device is enabled in ACPI mode */
  48         gnvs->dev.scc_en[nvs_index] = 1;
  49 }