src/soc/intel/braswell/lpc_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/io.h>
  16 #include <soc/gpio.h>
  17 #include <soc/pm.h>
  18 #include <device/mmio.h>
  19 #include <soc/iomap.h>
  20
  21 #define SUSPEND_CYCLE 1
  22 #define RESUME_CYCLE 0
  23 #define LPC_FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO)
  24 #define LPC_INTERNAL_PAD_NUM(gpio_pad) (gpio_pad %  MAX_FAMILY_PAD_GPIO_NO)
  25 #define LPC_GPIO_OFFSET(gpio_pad)  (FAMILY_PAD_REGS_OFF \
  26                   + (FAMILY_PAD_REGS_SIZE * LPC_FAMILY_NUMBER(gpio_pad) \
  27                   + (GPIO_REGS_SIZE * LPC_INTERNAL_PAD_NUM(gpio_pad))))
  28
  29 #define LPC_AD2_MMIO_OFFSET     LPC_GPIO_OFFSET(45)
  30 #define LPC_CLKRUN_MMIO_OFFSET  LPC_GPIO_OFFSET(46)
  31 #define LPC_AD0_MMIO_OFFSET     LPC_GPIO_OFFSET(47)
  32 #define LPC_FRAME_MMIO_OFFSET   LPC_GPIO_OFFSET(48)
  33 #define LPC_AD3_MMIO_OFFSET     LPC_GPIO_OFFSET(50)
  34 #define LPC_AD1_MMIO_OFFSET     LPC_GPIO_OFFSET(52)
  35
  36
  37 /* Value written into pad control reg 0 in early init */
  38 #define PAD_CFG0_NATIVE(mode, term, inv_rx_tx) (PAD_GPIO_DISABLE \
  39                                 | PAD_GPIOFG_HI_Z \
  40                                 | PAD_MODE_SELECTION(mode) | PAD_PULL(term))
  41
  42 #define PAD_CFG0_NATIVE_PU20K(mode) PAD_CFG0_NATIVE(mode, 9, 0) /* PU 20K */
  43 #define PAD_CFG0_NATIVE_PD20K(mode) PAD_CFG0_NATIVE(mode, 1, 0) /* PD 20K */
  44 #define PAD_CFG0_NATIVE_M1          PAD_CFG0_NATIVE(1, 0, 0)    /* no pull */
  45
  46 /*
  47  * Configure value in LPC GPIO PADCFG0 registers. This function would be called
  48  * to configure for low power/restore LPC GPIO lines
  49  */
  50 static void lpc_gpio_config(u32 cycle)
  51 {
  52         if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */
  53                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  54                                 LPC_FRAME_MMIO_OFFSET),
  55                                 PAD_CFG0_NATIVE_PU20K(1));
  56                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  57                                 LPC_AD0_MMIO_OFFSET),
  58                                 PAD_CFG0_NATIVE_PU20K(1));
  59                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  60                                 LPC_AD1_MMIO_OFFSET),
  61                                 PAD_CFG0_NATIVE_PU20K(1));
  62                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  63                                 LPC_AD2_MMIO_OFFSET),
  64                                 PAD_CFG0_NATIVE_PU20K(1));
  65                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  66                                 LPC_AD3_MMIO_OFFSET),
  67                                 PAD_CFG0_NATIVE_PU20K(1));
  68                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  69                                 LPC_CLKRUN_MMIO_OFFSET),
  70                                 PAD_CFG0_NATIVE_PD20K(1));
  71         } else { /* Resume cycle */
  72                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  73                                 LPC_FRAME_MMIO_OFFSET),
  74                                 PAD_CFG0_NATIVE_M1);
  75                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  76                                 LPC_AD0_MMIO_OFFSET),
  77                                 PAD_CFG0_NATIVE_PU20K(1));
  78                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  79                                 LPC_AD1_MMIO_OFFSET),
  80                                 PAD_CFG0_NATIVE_PU20K(1));
  81                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  82                                 LPC_AD2_MMIO_OFFSET),
  83                                 PAD_CFG0_NATIVE_PU20K(1));
  84                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  85                                 LPC_AD3_MMIO_OFFSET),
  86                                 PAD_CFG0_NATIVE_PU20K(1));
  87                 write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
  88                                 LPC_CLKRUN_MMIO_OFFSET),
  89                                 PAD_CFG0_NATIVE_M1);
  90         }
  91 }
  92
  93 /*
  94  * configure LPC GPIO lines for low power
  95  */
  96 void lpc_set_low_power(void)
  97 {
  98         lpc_gpio_config(SUSPEND_CYCLE);
  99 }
 100
 101 /*
 102  * Configure GPIO lines early during romstage.
 103  */
 104 void lpc_init(void)
 105 {
 106         uint16_t pm1_sts;
 107         uint32_t pm1_cnt;
 108         int slp_type = 0;
 109
 110         /*
 111          * On S3 resume re-initialize GPIO lines which were
 112          * configured for low power during S3 entry.
 113          */
 114         pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
 115         pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 116
 117         if (pm1_sts & WAK_STS)
 118                 slp_type = acpi_sleep_from_pm1(pm1_cnt);
 119
 120         if ((slp_type == ACPI_S3) || (slp_type == ACPI_S5))
 121                 lpc_gpio_config(RESUME_CYCLE);
 122 }