src/soc/intel/baytrail/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <device/mmio.h>
  16 #include <device/pci_ops.h>
  17 #include <soc/pci_devs.h>
  18 #include <soc/ramstage.h>
  19 #include <soc/sata.h>
  20 #include <console/console.h>
  21 #include <delay.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25
  26 #include "chip.h"
  27
  28 typedef struct soc_intel_baytrail_config config_t;
  29
  30 static inline void sir_write(struct device *dev, int idx, u32 value)
  31 {
  32         pci_write_config32(dev, SATA_SIRI, idx);
  33         pci_write_config32(dev, SATA_SIRD, value);
  34 }
  35
  36 static void sata_init(struct device *dev)
  37 {
  38         config_t *config = config_of(dev);
  39         u32 reg32;
  40         u16 reg16;
  41         u8  reg8;
  42
  43         printk(BIOS_DEBUG, "SATA: Initializing...\n");
  44
  45         if (!config->sata_ahci) {
  46                 /* Set legacy or native decoding mode */
  47                 if (config->ide_legacy_combined) {
  48                         reg8 = pci_read_config8(dev, 0x09);
  49                         reg8 &= ~0x5;
  50                         pci_write_config8(dev, 0x09, reg8);
  51                 } else {
  52                         reg8 = pci_read_config8(dev, 0x09);
  53                         reg8 |= 0x5;
  54                         pci_write_config8(dev, 0x09, reg8);
  55                 }
  56
  57                 /* Set capabilities pointer */
  58                 pci_write_config8(dev, 0x34, 0x70);
  59                 reg16 = pci_read_config16(dev, 0x70);
  60                 reg16 &= ~0xFF00;
  61                 pci_write_config16(dev, 0x70, reg16);
  62         }
  63
  64         /* Primary timing - decode enable */
  65         reg16 = pci_read_config16(dev, 0x40);
  66         reg16 |= 1 << 15;
  67         pci_write_config16(dev, 0x40, reg16);
  68
  69         /* Secondary timing - decode enable */
  70         reg16 = pci_read_config16(dev, 0x42);
  71         reg16 |= 1 << 15;
  72         pci_write_config16(dev, 0x42, reg16);
  73
  74         /* Port mapping enables */
  75         reg16 = pci_read_config16(dev, 0x90);
  76         reg16 |= (config->sata_port_map ^ 0x3) << 8;
  77         pci_write_config16(dev, 0x90, reg16);
  78
  79         /* Port control enables */
  80         reg16 = pci_read_config16(dev, 0x92);
  81         reg16 &= ~0x003f;
  82         reg16 |= config->sata_port_map;
  83         pci_write_config16(dev, 0x92, reg16);
  84
  85         if (config->sata_ahci) {
  86           u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
  87
  88                 /* Enable CR memory space decoding */
  89                 reg16 = pci_read_config16(dev, 0x04);
  90                 reg16 |= 0x2;
  91                 pci_write_config16(dev, 0x04, reg16);
  92
  93                 /* Set capability register */
  94                 reg32 = read32(abar + 0x00);
  95                 reg32 |= 0x0c046000;  // set PSC+SSC+SALP+SSS+SAM
  96                 reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits
  97                 reg32 |= (0x3 << 20); // Gen3 SATA
  98                 write32(abar + 0x00, reg32);
  99
 100                 /* Ports enabled */
 101                 reg32 = read32(abar + 0x0c);
 102                 reg32 &= (u32)(~0x3f);
 103                 reg32 |= config->sata_port_map;
 104                 write32(abar + 0xc, reg32);
 105                 /* Two extra reads to latch */
 106                 read32(abar + 0x0c);
 107                 read32(abar + 0x0c);
 108
 109                 /* Set cap2 - Support devslp */
 110                 reg32 = (1 << 5) | (1 << 4) | (1 << 3);
 111                 write32(abar + 0x24, reg32);
 112
 113                 /* Set PxCMD registers */
 114                 reg32 = read32(abar + 0x118);
 115                 reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) |
 116                         (1 << 19) | (1 << 18) | (1 << 1));
 117                 reg32 |= 2;
 118                 write32(abar + 0x118, reg32);
 119
 120                 reg32 = read32(abar + 0x198);
 121                 reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) |
 122                         (1 << 19) | (1 << 18) | (1 << 1));
 123                 reg32 |= 2;
 124                 write32(abar + 0x198, reg32);
 125
 126                 /* Clear reset features */
 127                 write32(abar + 0xc8, 0);
 128
 129                 /* Enable interrupts */
 130                 reg8 = read8(abar + 0x04);
 131                 reg8 |= 0x02;
 132                 write8(abar + 0x04, reg8);
 133
 134         } else {
 135                 /* TODO(shawnn): Configure IDE SATA speed regs */
 136         }
 137
 138         /* 1.4 us delay after configuring port / enable bits */
 139         udelay(2);
 140
 141         /* Enable clock for ports */
 142         reg32 = pci_read_config32(dev, 0x94);
 143         reg32 |= 0x3f << 24;
 144         pci_write_config32(dev, 0x94, reg32);
 145         reg32 &= (config->sata_port_map ^ 0x3) << 24;
 146         pci_write_config32(dev, 0x94, reg32);
 147
 148         /* Lock SataGc register */
 149         reg32 = (0x1 << 31) | (0x7 << 12);
 150         pci_write_config32(dev, 0x98, reg32);
 151 }
 152
 153 static void sata_enable(struct device *dev)
 154 {
 155         config_t *config = config_of(dev);
 156         u8  reg8;
 157         u16 reg16;
 158         u32 reg32;
 159
 160         southcluster_enable_dev(dev);
 161
 162         /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */
 163         reg16 = pci_read_config16(dev, 0x90);
 164         reg16 &= ~0x03e0;
 165         reg16 |= (config->sata_port_map ^ 0x3) << 8;
 166         if (config->sata_ahci)
 167                 reg16 |= 0x60;
 168         pci_write_config16(dev, 0x90, reg16);
 169
 170         /* Set reg 0x94 before starting configuration */
 171         reg32 = pci_read_config32(dev, 0x94);
 172         reg32 &= (u32)(~0x1ff);
 173         reg32 |= 0x183;
 174         pci_write_config32(dev, 0x94, reg32);
 175
 176         /* Set ORM bit */
 177         reg16 = pci_read_config16(dev, 0x92);
 178         reg16 |= (1 << 15);
 179         pci_write_config16(dev, 0x92, reg16);
 180
 181         /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */
 182         reg32 = pci_read_config32(dev, 0x98);
 183         reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5));
 184         reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) |
 185                  (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5);
 186         pci_write_config32(dev, 0x98, reg32);
 187
 188         /* CMD reg - set bus master enable (BME) */
 189         reg8 = pci_read_config8(dev, 0x04);
 190         reg8 |= (1 << 2);
 191         pci_write_config8(dev, 0x04, reg8);
 192
 193         /* "Test mode registers" */
 194         sir_write(dev, 0x70, 0x00288301);
 195         sir_write(dev, 0x54, 0x00000300);
 196         sir_write(dev, 0x58, 0x50000000);
 197         /* "OOB Detection Margin */
 198         sir_write(dev, 0x6c, 0x130C0603);
 199         /* "Gasket Control" */
 200         sir_write(dev, 0xf4, 0);
 201
 202         /* PCS - Enable requested SATA ports */
 203         reg8 = pci_read_config8(dev, 0x92);
 204         reg8 &= ~0x03;
 205         reg8 |= config->sata_port_map;
 206         pci_write_config8(dev, 0x92, reg8);
 207 }
 208
 209 static struct device_operations sata_ops = {
 210         .read_resources         = pci_dev_read_resources,
 211         .set_resources          = pci_dev_set_resources,
 212         .enable_resources       = pci_dev_enable_resources,
 213         .init                   = sata_init,
 214         .enable                 = sata_enable,
 215         .scan_bus               = NULL,
 216         .ops_pci                = &soc_pci_ops,
 217 };
 218
 219 static const unsigned short pci_device_ids[] = {
 220         IDE1_DEVID, IDE2_DEVID,                 /* IDE */
 221         AHCI1_DEVID, AHCI2_DEVID,               /* AHCI */
 222         0,
 223 };
 224
 225 static const struct pci_driver baytrail_sata __pci_driver = {
 226         .ops     = &sata_ops,
 227         .vendor  = PCI_VENDOR_ID_INTEL,
 228         .devices = pci_device_ids,
 229 };