src/soc/intel/baytrail/include/soc/xhci.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef BAYTRAIL_XHCI_H
  16 #define BAYTRAIL_XHCI_H
  17
  18 /* XHCI PCI Registers */
  19 #define XHCI_PWR_CTL_STS        0x74
  20 #define XHCI_USB2PR             0xd0
  21 #define XHCI_USB2PRM            0xd4
  22 #define XHCI_USB3PR             0xd8
  23 #define XHCI_USB3PRM            0xdc
  24 #define XHCI_USB2PDO            0xe4
  25 #define XHCI_USB3PDO            0xe8
  26
  27 /* XHCI Memory Registers */
  28 #define XHCI_USB3_PORTSC(port)  (0x4e0 + (port * 0x10))
  29 # define  XHCI_USB3_PORTSC_CHST   (0x7f << 17)
  30 # define  XHCI_USB3_PORTSC_WCE    (1 << 25)  /* Wake on Connect */
  31 # define  XHCI_USB3_PORTSC_WDE    (1 << 26)  /* Wake on Disconnect */
  32 # define  XHCI_USB3_PORTSC_WOE    (1 << 27)  /* Wake on Overcurrent */
  33 # define  XHCI_USB3_PORTSC_WRC    (1 << 19)  /* Warm Reset Complete */
  34 # define  XHCI_USB3_PORTSC_LWS    (1 << 16)  /* Link Write Strobe */
  35 # define  XHCI_USB3_PORTSC_PED    (1 << 1)   /* Port Enabled/Disabled */
  36 # define  XHCI_USB3_PORTSC_WPR    (1 << 31)  /* Warm Port Reset */
  37 # define  XHCI_USB3_PORTSC_PLS    (0xf << 5) /* Port Link State */
  38 # define   XHCI_PLSR_DISABLED     (4 << 5)   /* Port is disabled */
  39 # define   XHCI_PLSR_RXDETECT     (5 << 5)   /* Port is disconnected */
  40 # define   XHCI_PLSR_POLLING      (7 << 5)   /* Port is polling */
  41 # define   XHCI_PLSW_ENABLE       (5 << 5)   /* Enable port */
  42
  43 /* The Fuse register is incorrect for Baytrail-M so use hardcoded values */
  44 #define BYTM_USB2_PORT_COUNT    4
  45 #define BYTM_USB2_PORT_MAP      0xf
  46 #define BYTM_USB3_PORT_COUNT    1
  47 #define BYTM_USB3_PORT_MAP      0x1
  48
  49 #define XHCI_RESET_TIMEOUT      100000  /* 100ms */
  50
  51 #endif /* BAYTRAIL_XHCI_H */