src/soc/intel/baytrail/bootblock/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/bootblock.h>
  16 #include <device/pci_ops.h>
  17 #include <soc/iosf.h>
  18 #include <soc/iomap.h>
  19 #include <soc/gpio.h>
  20 #include <soc/lpc.h>
  21 #include <soc/spi.h>
  22 #include <soc/pmc.h>
  23
  24 static void setup_mmconfig(void)
  25 {
  26         uint32_t reg;
  27
  28         /* Set up the MMCONF range. The register lives in the BUNIT. The
  29          * IO variant of the config access needs to be used initially to
  30          * properly configure as the IOSF access registers live in PCI
  31          * config space. */
  32         reg = 0;
  33         /* Clear the extended register. */
  34         pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
  35         reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
  36         pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
  37         reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
  38               IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
  39         pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
  40 }
  41
  42 static void program_base_addresses(void)
  43 {
  44         uint32_t reg;
  45         const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
  46
  47         /* Memory Mapped IO registers. */
  48         reg = PMC_BASE_ADDRESS | 2;
  49         pci_write_config32(lpc_dev, PBASE, reg);
  50         reg = IO_BASE_ADDRESS | 2;
  51         pci_write_config32(lpc_dev, IOBASE, reg);
  52         reg = ILB_BASE_ADDRESS | 2;
  53         pci_write_config32(lpc_dev, IBASE, reg);
  54         reg = SPI_BASE_ADDRESS | 2;
  55         pci_write_config32(lpc_dev, SBASE, reg);
  56         reg = MPHY_BASE_ADDRESS | 2;
  57         pci_write_config32(lpc_dev, MPBASE, reg);
  58         reg = PUNIT_BASE_ADDRESS | 2;
  59         pci_write_config32(lpc_dev, PUBASE, reg);
  60         reg = RCBA_BASE_ADDRESS | 1;
  61         pci_write_config32(lpc_dev, RCBA, reg);
  62
  63         /* IO Port Registers. */
  64         reg = ACPI_BASE_ADDRESS | 2;
  65         pci_write_config32(lpc_dev, ABASE, reg);
  66         reg = GPIO_BASE_ADDRESS | 2;
  67         pci_write_config32(lpc_dev, GBASE, reg);
  68 }
  69
  70 static void spi_init(void)
  71 {
  72         u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
  73         u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
  74         uint32_t reg;
  75
  76         /* Disable generating SMI when setting WPD bit. */
  77         write32(scs, read32(scs) & ~SMIWPEN);
  78         /*
  79          * Enable caching and prefetching in the SPI controller. Disable
  80          * the SMM-only BIOS write and set WPD bit.
  81          */
  82         reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
  83         reg &= ~EISS;
  84         write32(bcr, reg);
  85 }
  86
  87 static void tco_disable(void)
  88 {
  89         uint32_t reg;
  90
  91         reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
  92         reg |= TCO_TMR_HALT;
  93         outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
  94 }
  95
  96 static void byt_config_com1_and_enable(void)
  97 {
  98         uint32_t reg;
  99
 100         /* Enable the UART hardware for COM1. */
 101         reg = 1;
 102         pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
 103
 104         /* Set up the pads to select the UART function */
 105         score_select_func(UART_RXD_PAD, 1);
 106         score_select_func(UART_TXD_PAD, 1);
 107 }
 108
 109 /* The distinction between nb/sb/cpu is not applicable here so
 110    just pick the one that is called first. */
 111 void bootblock_early_northbridge_init(void)
 112 {
 113         /* Allow memory-mapped PCI config access. */
 114         setup_mmconfig();
 115
 116         program_base_addresses();
 117
 118         tco_disable();
 119
 120         if (CONFIG(ENABLE_BUILTIN_COM1))
 121                 byt_config_com1_and_enable();
 122
 123         spi_init();
 124 }