src/soc/intel/baytrail/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/acpi.h>
  16 #include <arch/acpigen.h>
  17 #include <device/mmio.h>
  18 #include <arch/smp/mpspec.h>
  19 #include <cbmem.h>
  20 #include <console/console.h>
  21 #include <cpu/x86/smm.h>
  22 #include <types.h>
  23 #include <cpu/x86/msr.h>
  24 #include <cpu/x86/tsc.h>
  25 #include <cpu/intel/turbo.h>
  26
  27 #include <soc/acpi.h>
  28 #include <soc/iomap.h>
  29 #include <soc/irq.h>
  30 #include <soc/msr.h>
  31 #include <soc/pattrs.h>
  32 #include <soc/pmc.h>
  33
  34 #include <ec/google/chromeec/ec.h>
  35 #include <vendorcode/google/chromeos/gnvs.h>
  36
  37 #define MWAIT_RES(state, sub_state)                         \
  38         {                                                   \
  39                 .addrl = (((state) << 4) | (sub_state)),    \
  40                 .space_id = ACPI_ADDRESS_SPACE_FIXED,       \
  41                 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,    \
  42                 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,    \
  43                 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
  44         }
  45
  46 /* C-state map without S0ix */
  47 static acpi_cstate_t cstate_map[] = {
  48         {
  49                 /* C1 */
  50                 .ctype = 1, /* ACPI C1 */
  51                 .latency = 1,
  52                 .power = 1000,
  53                 .resource = MWAIT_RES(0, 0),
  54         },
  55         {
  56                 /* C6NS with no L2 shrink */
  57                 /* NOTE: this substate is above CPUID limit */
  58                 .ctype = 2, /* ACPI C2 */
  59                 .latency = 500,
  60                 .power = 10,
  61                 .resource = MWAIT_RES(5, 1),
  62         },
  63         {
  64                 /* C6FS with full L2 shrink */
  65                 .ctype = 3, /* ACPI C3 */
  66                 .latency = 1500, /* 1.5ms worst case */
  67                 .power = 1,
  68                 .resource = MWAIT_RES(5, 2),
  69         }
  70 };
  71
  72 void acpi_init_gnvs(global_nvs_t *gnvs)
  73 {
  74         /* Set unknown wake source */
  75         gnvs->pm1i = -1;
  76
  77         /* CPU core count */
  78         gnvs->pcnt = dev_count_cpu();
  79
  80         /* Top of Low Memory (start of resource allocation) */
  81         gnvs->tolm = nc_read_top_of_low_memory();
  82
  83 #if CONFIG(CONSOLE_CBMEM)
  84         /* Update the mem console pointer. */
  85         gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
  86 #endif
  87
  88 #if CONFIG(CHROMEOS)
  89         /* Initialize Verified Boot data */
  90         chromeos_init_chromeos_acpi(&(gnvs->chromeos));
  91 #if CONFIG(EC_GOOGLE_CHROMEEC)
  92         gnvs->chromeos.vbt2 = google_ec_running_ro() ?
  93                 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
  94 #endif
  95 #endif
  96 }
  97
  98 static int acpi_sci_irq(void)
  99 {
 100         u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
 101         int scis;
 102         static int sci_irq;
 103
 104         if (sci_irq)
 105                 return sci_irq;
 106
 107         /* Determine how SCI is routed. */
 108         scis = read32(actl) & SCIS_MASK;
 109         switch (scis) {
 110         case SCIS_IRQ9:
 111         case SCIS_IRQ10:
 112         case SCIS_IRQ11:
 113                 sci_irq = scis - SCIS_IRQ9 + 9;
 114                 break;
 115         case SCIS_IRQ20:
 116         case SCIS_IRQ21:
 117         case SCIS_IRQ22:
 118         case SCIS_IRQ23:
 119                 sci_irq = scis - SCIS_IRQ20 + 20;
 120                 break;
 121         default:
 122                 printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
 123                 sci_irq = 9;
 124                 break;
 125         }
 126
 127         printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
 128         return sci_irq;
 129 }
 130
 131 unsigned long acpi_fill_mcfg(unsigned long current)
 132 {
 133         current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
 134                                              MCFG_BASE_ADDRESS, 0, 0, 255);
 135         return current;
 136 }
 137
 138 void acpi_fill_in_fadt(acpi_fadt_t *fadt)
 139 {
 140         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 141
 142         fadt->sci_int = acpi_sci_irq();
 143         fadt->smi_cmd = APM_CNT;
 144         fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
 145         fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
 146         fadt->s4bios_req = 0x0;
 147         fadt->pstate_cnt = 0;
 148
 149         fadt->pm1a_evt_blk = pmbase + PM1_STS;
 150         fadt->pm1b_evt_blk = 0x0;
 151         fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
 152         fadt->pm1b_cnt_blk = 0x0;
 153         fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK;
 154         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 155         fadt->gpe0_blk = pmbase + GPE0_STS;
 156         fadt->gpe1_blk = 0;
 157
 158         fadt->pm1_evt_len = 4;
 159         fadt->pm1_cnt_len = 2;
 160         fadt->pm2_cnt_len = 1;
 161         fadt->pm_tmr_len = 4;
 162         fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
 163         fadt->gpe1_blk_len = 0;
 164         fadt->gpe1_base = 0;
 165         fadt->cst_cnt = 0;
 166         fadt->p_lvl2_lat = 1;
 167         fadt->p_lvl3_lat = 87;
 168         fadt->flush_size = 1024;
 169         fadt->flush_stride = 16;
 170         fadt->duty_offset = 1;
 171         fadt->duty_width = 0;
 172         fadt->day_alrm = 0xd;
 173         fadt->mon_alrm = 0x00;
 174         fadt->century = 0x00;
 175         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
 176
 177         fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
 178                         ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
 179                         ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
 180                         ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 181
 182         fadt->reset_reg.space_id = 1;
 183         fadt->reset_reg.bit_width = 8;
 184         fadt->reset_reg.bit_offset = 0;
 185         fadt->reset_reg.access_size = 0;
 186         fadt->reset_reg.addrl = 0xcf9;
 187         fadt->reset_reg.addrh = 0;
 188         fadt->reset_value = 6;
 189
 190         fadt->x_pm1a_evt_blk.space_id = 1;
 191         fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
 192         fadt->x_pm1a_evt_blk.bit_offset = 0;
 193         fadt->x_pm1a_evt_blk.access_size = 0;
 194         fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
 195         fadt->x_pm1a_evt_blk.addrh = 0x0;
 196
 197         fadt->x_pm1b_evt_blk.space_id = 1;
 198         fadt->x_pm1b_evt_blk.bit_width = 0;
 199         fadt->x_pm1b_evt_blk.bit_offset = 0;
 200         fadt->x_pm1b_evt_blk.access_size = 0;
 201         fadt->x_pm1b_evt_blk.addrl = 0x0;
 202         fadt->x_pm1b_evt_blk.addrh = 0x0;
 203
 204         fadt->x_pm1a_cnt_blk.space_id = 1;
 205         fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
 206         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 207         fadt->x_pm1a_cnt_blk.access_size = 0;
 208         fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
 209         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 210
 211         fadt->x_pm1b_cnt_blk.space_id = 1;
 212         fadt->x_pm1b_cnt_blk.bit_width = 0;
 213         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 214         fadt->x_pm1b_cnt_blk.access_size = 0;
 215         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 216         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 217
 218         fadt->x_pm2_cnt_blk.space_id = 1;
 219         fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
 220         fadt->x_pm2_cnt_blk.bit_offset = 0;
 221         fadt->x_pm2_cnt_blk.access_size = 0;
 222         fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK;
 223         fadt->x_pm2_cnt_blk.addrh = 0x0;
 224
 225         fadt->x_pm_tmr_blk.space_id = 1;
 226         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 227         fadt->x_pm_tmr_blk.bit_offset = 0;
 228         fadt->x_pm_tmr_blk.access_size = 0;
 229         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 230         fadt->x_pm_tmr_blk.addrh = 0x0;
 231
 232         fadt->x_gpe0_blk.space_id = 1;
 233         fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
 234         fadt->x_gpe0_blk.bit_offset = 0;
 235         fadt->x_gpe0_blk.access_size = 0;
 236         fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
 237         fadt->x_gpe0_blk.addrh = 0x0;
 238
 239         fadt->x_gpe1_blk.space_id = 1;
 240         fadt->x_gpe1_blk.bit_width = 0;
 241         fadt->x_gpe1_blk.bit_offset = 0;
 242         fadt->x_gpe1_blk.access_size = 0;
 243         fadt->x_gpe1_blk.addrl = 0x0;
 244         fadt->x_gpe1_blk.addrh = 0x0;
 245 }
 246
 247 static acpi_tstate_t baytrail_tss_table[] = {
 248         { 100, 1000, 0, 0x00, 0 },
 249         { 88, 875, 0, 0x1e, 0 },
 250         { 75, 750, 0, 0x1c, 0 },
 251         { 63, 625, 0, 0x1a, 0 },
 252         { 50, 500, 0, 0x18, 0 },
 253         { 38, 375, 0, 0x16, 0 },
 254         { 25, 250, 0, 0x14, 0 },
 255         { 13, 125, 0, 0x12, 0 },
 256 };
 257
 258 static void generate_T_state_entries(int core, int cores_per_package)
 259 {
 260         /* Indicate SW_ALL coordination for T-states */
 261         acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
 262
 263         /* Indicate FFixedHW so OS will use MSR */
 264         acpigen_write_empty_PTC();
 265
 266         /* Set NVS controlled T-state limit */
 267         acpigen_write_TPC("\\TLVL");
 268
 269         /* Write TSS table for MSR access */
 270         acpigen_write_TSS_package(
 271                 ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table);
 272 }
 273
 274 static int calculate_power(int tdp, int p1_ratio, int ratio)
 275 {
 276         u32 m;
 277         u32 power;
 278
 279         /*
 280          * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
 281          *
 282          * Power = (ratio / p1_ratio) * m * tdp
 283          */
 284
 285         m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
 286         m = (m * m) / 1000;
 287
 288         power = ((ratio * 100000 / p1_ratio) / 100);
 289         power *= (m / 100) * (tdp / 1000);
 290         power /= 1000;
 291
 292         return (int)power;
 293 }
 294
 295 static void generate_P_state_entries(int core, int cores_per_package)
 296 {
 297         int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
 298         int coord_type, power_max, power_unit, num_entries;
 299         int ratio, power, clock, clock_max;
 300         int vid, vid_turbo, vid_min, vid_max, vid_range_2;
 301         u32 control_status;
 302         const struct pattrs *pattrs = pattrs_get();
 303         msr_t msr;
 304
 305         /* Inputs from CPU attributes */
 306         ratio_max = pattrs->iacore_ratios[IACORE_MAX];
 307         ratio_min = pattrs->iacore_ratios[IACORE_LFM];
 308         vid_max = pattrs->iacore_vids[IACORE_MAX];
 309         vid_min = pattrs->iacore_vids[IACORE_LFM];
 310
 311         /* Set P-states coordination type based on MSR disable bit */
 312         coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL;
 313
 314         /* Max Non-Turbo Frequency */
 315         clock_max = (ratio_max * pattrs->bclk_khz) / 1000;
 316
 317         /* Calculate CPU TDP in mW */
 318         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 319         power_unit = 1 << (msr.lo & 0xf);
 320         msr = rdmsr(MSR_PKG_POWER_LIMIT);
 321         power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
 322
 323         /* Write _PCT indicating use of FFixedHW */
 324         acpigen_write_empty_PCT();
 325
 326         /* Write _PPC with NVS specified limit on supported P-state */
 327         acpigen_write_PPC_NVS();
 328
 329         /* Write PSD indicating configured coordination type */
 330         acpigen_write_PSD_package(core, 1, coord_type);
 331
 332         /* Add P-state entries in _PSS table */
 333         acpigen_write_name("_PSS");
 334
 335         /* Determine ratio points */
 336         ratio_step = 1;
 337         num_entries = (ratio_max - ratio_min) / ratio_step;
 338         while (num_entries > 15) { /* ACPI max is 15 ratios */
 339                 ratio_step <<= 1;
 340                 num_entries >>= 1;
 341         }
 342
 343         /* P[T] is Turbo state if enabled */
 344         if (get_turbo_state() == TURBO_ENABLED) {
 345                 /* _PSS package count including Turbo */
 346                 acpigen_write_package(num_entries + 2);
 347
 348                 ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
 349                 vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
 350                 control_status = (ratio_turbo << 8) | vid_turbo;
 351
 352                 /* Add entry for Turbo ratio */
 353                 acpigen_write_PSS_package(
 354                         clock_max + 1,          /*MHz*/
 355                         power_max,              /*mW*/
 356                         10,                     /*lat1*/
 357                         10,                     /*lat2*/
 358                         control_status,         /*control*/
 359                         control_status);        /*status*/
 360         } else {
 361                 /* _PSS package count without Turbo */
 362                 acpigen_write_package(num_entries + 1);
 363                 ratio_turbo = ratio_max;
 364                 vid_turbo = vid_max;
 365         }
 366
 367         /* First regular entry is max non-turbo ratio */
 368         control_status = (ratio_max << 8) | vid_max;
 369         acpigen_write_PSS_package(
 370                 clock_max,              /*MHz*/
 371                 power_max,              /*mW*/
 372                 10,                     /*lat1*/
 373                 10,                     /*lat2*/
 374                 control_status,         /*control */
 375                 control_status);        /*status*/
 376
 377         /* Set up ratio and vid ranges for VID calculation */
 378         ratio_range_2 = (ratio_turbo - ratio_min) * 2;
 379         vid_range_2 = (vid_turbo - vid_min) * 2;
 380
 381         /* Generate the remaining entries */
 382         for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 383              ratio >= ratio_min; ratio -= ratio_step) {
 384
 385                 /* Calculate VID for this ratio */
 386                 vid = ((ratio - ratio_min) * vid_range_2) /
 387                         ratio_range_2 + vid_min;
 388                 /* Round up if remainder */
 389                 if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
 390                         vid++;
 391
 392                 /* Calculate power at this ratio */
 393                 power = calculate_power(power_max, ratio_max, ratio);
 394                 clock = (ratio * pattrs->bclk_khz) / 1000;
 395                 control_status = (ratio << 8) | (vid & 0xff);
 396
 397                 acpigen_write_PSS_package(
 398                         clock,                  /*MHz*/
 399                         power,                  /*mW*/
 400                         10,                     /*lat1*/
 401                         10,                     /*lat2*/
 402                         control_status,         /*control*/
 403                         control_status);        /*status*/
 404         }
 405
 406         /* Fix package length */
 407         acpigen_pop_len();
 408 }
 409
 410 void generate_cpu_entries(struct device *device)
 411 {
 412         int core;
 413         int pcontrol_blk = get_pmbase(), plen = 6;
 414         const struct pattrs *pattrs = pattrs_get();
 415
 416         for (core = 0; core < pattrs->num_cpus; core++) {
 417                 if (core > 0) {
 418                         pcontrol_blk = 0;
 419                         plen = 0;
 420                 }
 421
 422                 /* Generate processor \_PR.CPUx */
 423                 acpigen_write_processor(
 424                         core, pcontrol_blk, plen);
 425
 426                 /* Generate  P-state tables */
 427                 generate_P_state_entries(
 428                         core, pattrs->num_cpus);
 429
 430                 /* Generate C-state tables */
 431                 acpigen_write_CST_package(
 432                         cstate_map, ARRAY_SIZE(cstate_map));
 433
 434                 /* Generate T-state tables */
 435                 generate_T_state_entries(
 436                         core, pattrs->num_cpus);
 437
 438                 acpigen_pop_len();
 439         }
 440
 441         /* PPKG is usually used for thermal management
 442            of the first and only package. */
 443         acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus);
 444
 445         /* Add a method to notify processor nodes */
 446         acpigen_write_processor_cnot(pattrs->num_cpus);
 447 }
 448
 449 unsigned long acpi_madt_irq_overrides(unsigned long current)
 450 {
 451         int sci_irq = acpi_sci_irq();
 452         acpi_madt_irqoverride_t *irqovr;
 453         uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
 454
 455         /* INT_SRC_OVR */
 456         irqovr = (void *)current;
 457         current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
 458
 459         if (sci_irq >= 20)
 460                 sci_flags |= MP_IRQ_POLARITY_LOW;
 461         else
 462                 sci_flags |= MP_IRQ_POLARITY_HIGH;
 463
 464         irqovr = (void *)current;
 465         current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
 466                                                 sci_flags);
 467
 468         return current;
 469 }