src/soc/cavium/common/ecam.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
  15  */
  16
  17 #define __SIMPLE_DEVICE__
  18
  19 #include <device/pci_ops.h>
  20 #include <device/pci_def.h>
  21 #include <device/pci.h>
  22 #include <soc/addressmap.h>
  23 #include <soc/ecam.h>
  24
  25 /**
  26  * Get PCI BAR address from cavium specific extended capability.
  27  * Use regular BAR if not found in extended capability space.
  28  *
  29  * @return The physical address of the BAR, zero on error
  30  */
  31 uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar)
  32 {
  33         size_t cap_offset = pci_s_find_capability(dev, 0x14);
  34         uint64_t h, l, ret = 0;
  35         if (cap_offset) {
  36                 /* Found EA */
  37                 u8 es, bei;
  38                 u8 ne = pci_read_config8(dev, cap_offset + 2) & 0x3f;
  39
  40                 cap_offset += 4;
  41                 while (ne) {
  42                         uint32_t dw0 = pci_read_config32(dev, cap_offset);
  43
  44                         es = dw0 & 7;
  45                         bei = (dw0 >> 4) & 0xf;
  46                         if (bei == bar) {
  47                                 h = 0;
  48                                 l = pci_read_config32(dev, cap_offset + 4);
  49                                 if (l & 2)
  50                                         h = pci_read_config32(dev,
  51                                                               cap_offset + 12);
  52                                 ret = (h << 32) | (l & ~0xfull);
  53                                 break;
  54                         }
  55                         cap_offset += (es + 1) * 4;
  56                         ne--;
  57                 }
  58         } else {
  59                 h = 0;
  60                 l = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0);
  61                 if (l & 4)
  62                         h = pci_read_config32(dev, bar * 4 + PCI_BASE_ADDRESS_0
  63                                               + 4);
  64                 ret = (h << 32) | (l & ~0xfull);
  65         }
  66         return ret;
  67 }