src/soc/amd/stoneyridge/include/soc/pci_devs.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
  16 #define __PI_STONEYRIDGE_PCI_DEVS_H__
  17
  18 #include <device/pci_def.h>
  19
  20 #if !defined(__SIMPLE_DEVICE__)
  21 #include <device/device.h>
  22 #define _SOC_DEV(slot, func)    pcidev_on_root(slot, func)
  23 #else
  24 #define _SOC_DEV(slot, func)    PCI_DEV(0, slot, func)
  25 #endif
  26
  27 /* GNB Root Complex */
  28 #define GNB_DEV                 0x0
  29 #define GNB_FUNC                0
  30 #define GNB_DEVID               0x1576
  31 #define GNB_DEVFN               PCI_DEVFN(GNB_DEV, GNB_FUNC)
  32 #define SOC_GNB_DEV             _SOC_DEV(GNB_DEV, GNB_FUNC)
  33
  34 /* IOMMU */
  35 #define IOMMU_DEV               0x0
  36 #define IOMMU_FUNC              2
  37 #define IOMMU_DEVID             0x1577
  38 #define IOMMU_DEVFN             PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
  39 #define SOC_IOMMU_DEV           _SOC_DEV(IOMMU_DEV, IOMMU_FUNC)
  40
  41 /*
  42  * Internal Graphics
  43  * Device IDs subject to SKU/OPN variation
  44  * GFX_DEVID for merlinfalcon           PCI_DEVICE_ID_AMD_15H_MODEL_606F_GFX
  45  * GFX_DEVID for stoneyridge            PCI_DEVICE_ID_AMD_15H_MODEL_707F_GFX
  46  */
  47 #define GFX_DEV                 0x1
  48 #define GFX_FUNC                0
  49 #define GFX_DEVFN               PCI_DEVFN(GFX_DEV, GFX_FUNC)
  50 #define SOC_GFX_DEV             _SOC_DEV(GFX_DEV, GFX_FUNC)
  51
  52 /* HD Audio 0
  53  * Device IDs
  54  * HDA0_DEVID                   PCI_DEVICE_ID_AMD_15H_MODEL_606F_HDA
  55  * HDA0_DEVID                   PCI_DEVICE_ID_AMD_15H_MODEL_707F_HDA
  56  */
  57 #define HDA0_DEV                0x1
  58 #define HDA0_FUNC               1
  59 #define HDA0_DEVFN              PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
  60 #define SOC_HDA0_DEV            _SOC_DEV(HDA0_DEV, HDA0_FUNC)
  61
  62 /* Host Bridge */
  63 #define HOST_DEV                0x2
  64 #define HOST_FUNC               0
  65 #define HOST_DEVID              0x157b
  66 #define HOST_DEVFN              PCI_DEVFN(HOST_DEV, HOST_FUNC)
  67 #define SOC_HOST_DEV            _SOC_DEV(HOST_DEV, HOST_FUNC)
  68
  69 /* PCIe GPP Bridge 0 */
  70 #define PCIE0_DEV               0x2
  71 #define PCIE0_FUNC              1
  72 #define PCIE0_DEVID             0x157c
  73 #define PCIE0_DEVFN             PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)
  74 #define SOC_PCIE0_DEV           _SOC_DEV(PCIE0_DEV, PCIE0_FUNC)
  75
  76 /* PCIe GPP Bridge 1 */
  77 #define PCIE1_DEV               0x2
  78 #define PCIE1_FUNC              2
  79 #define PCIE1_DEVID             0x157c
  80 #define PCIE1_DEVFN             PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)
  81 #define SOC_PCIE1_DEV           _SOC_DEV(PCIE1_DEV, PCIE1_FUNC)
  82
  83 /* PCIe GPP Bridge 2 */
  84 #define PCIE2_DEV               0x2
  85 #define PCIE2_FUNC              3
  86 #define PCIE2_DEVID             0x157c
  87 #define PCIE2_DEVFN             PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)
  88 #define SOC_PCIE2_DEV           _SOC_DEV(PCIE2_DEV, PCIE2_FUNC)
  89
  90 /* PCIe GPP Bridge 3 */
  91 #define PCIE3_DEV               0x2
  92 #define PCIE3_FUNC              4
  93 #define PCIE3_DEVID             0x157c
  94 #define PCIE3_DEVFN             PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)
  95 #define SOC_PCIE3_DEV           _SOC_DEV(PCIE3_DEV, PCIE3_FUNC)
  96
  97 /* PCIe GPP Bridge 4 */
  98 #define PCIE4_DEV               0x2
  99 #define PCIE4_FUNC              5
 100 #define PCIE4_DEVID             0x157c
 101 #define PCIE4_DEVFN             PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
 102 #define SOC_PCIE4_DEV           _SOC_DEV(PCIE4_DEV, PCIE4_FUNC)
 103
 104 /* Platform Security Processor */
 105 #define PSP_DEV                 0x8
 106 #define PSP_FUNC                0
 107 #define PSP_DEVID               0x1578
 108 #define PSP_DEVFN               PCI_DEVFN(PSP_DEV, PSP_FUNC)
 109 #define SOC_PSP_DEV             _SOC_DEV(PSP_DEV, PSP_FUNC)
 110
 111 /* HD Audio 1 */
 112 #define HDA1_DEV                0x9
 113 #define HDA1_FUNC               2
 114 #define HDA1_DEVID              0x157a
 115 #define HDA1_DEVFN              PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
 116 #define SOC_HDA1_DEV            _SOC_DEV(HDA1_DEV, HDA1_FUNC)
 117
 118 /* HT Configuration
 119  * Device IDs
 120  * HT_DEVID for merlinfalcon    PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT
 121  * HT_DEVID for stoneyridge     PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT
 122  */
 123 #define HT_DEV                  0x18
 124 #define HT_FUNC                 0
 125 #define HT_DEVFN                PCI_DEVFN(HT_DEV, HT_FUNC)
 126 #define SOC_HT_DEV              _SOC_DEV(HT_DEV, HT_FUNC)
 127
 128 /* Address Maps
 129  * Device IDs
 130  * ADDR_DEVID for merlinfalcon  0x1571
 131  * ADDR_DEVID for stoneyridge   0x15b1
 132  */
 133 #define ADDR_DEV                0x18
 134 #define ADDR_FUNC               1
 135 #define ADDR_DEVFN              PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
 136 #define SOC_ADDR_DEV            _SOC_DEV(ADDR_DEV, ADDR_FUNC)
 137
 138 /* DRAM Configuration
 139  * Device IDs
 140  * DCT_DEVID for merlinfalcon   0x1572
 141  * DCT_DEVID for stoneyridge    0x15b2
 142  */
 143 #define DCT_DEV                 0x18
 144 #define DCT_FUNC                2
 145 #define DCT_DEVFN               PCI_DEVFN(DCT_DEV, DCT_FUNC)
 146 #define SOC_DCT_DEV             _SOC_DEV(DCT_DEV, DCT_FUNC)
 147
 148 /* Misc. Configuration
 149  * Device IDs
 150  * MISC_DEVID for merlinfalcon  0x1573
 151  * MISC_DEVID for stoneyridge   0x15b3
 152  */
 153 #define MISC_DEV                0x18
 154 #define MISC_FUNC               3
 155 #define MISC_DEVFN              PCI_DEVFN(MISC_DEV, MISC_FUNC)
 156 #define SOC_MISC_DEV            _SOC_DEV(MISC_DEV, MISC_FUNC)
 157
 158 /* PM Configuration
 159  * Device IDs
 160  * PM_DEVID for merlinfalcon    0x1574
 161  * PM_DEVID for stoneyridge     0x15b4
 162  */
 163 #define PM_DEV                  0x18
 164 #define PM_FUNC                 4
 165 #define PM_DEVFN                PCI_DEVFN(PM_DEV, PM_FUNC)
 166 #define SOC_PM_DEV              _SOC_DEV(PM_DEV, PM_FUNC)
 167
 168 /* Northbridge Configuration
 169  * Device IDs
 170  * NB_DEVID for merlinfalcon    0x1575
 171  * NB_DEVID for stoneyridge     0x15b5
 172  */
 173 #define NB_DEV                  0x18
 174 #define NB_FUNC                 5
 175 #define NB_DEVFN                PCI_DEVFN(NB_DEV, NB_FUNC)
 176 #define SOC_NB_DEV              _SOC_DEV(NB_DEV, NB_FUNC)
 177
 178 /* XHCI */
 179 #define XHCI_DEV                0x10
 180 #define XHCI_FUNC               0
 181 #define XHCI_DEVID              0x7914
 182 #define XHCI_DEVFN              PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
 183 #define SOC_XHCI_DEV            _SOC_DEV(XHCI_DEV, XHCI_FUNC)
 184
 185 /* SATA */
 186 #define SATA_DEV                0x11
 187 #define SATA_FUNC               0
 188 #define SATA_IDE_DEVID          0x7900
 189 #define AHCI_DEVID_MS           0x7901
 190 #define AHCI_DEVID_AMD          0x7904
 191 #define SATA_DEVFN              PCI_DEVFN(SATA_DEV, SATA_FUNC)
 192 #define SOC_SATA_DEV            _SOC_DEV(SATA_DEV, SATA_FUNC)
 193
 194 /* EHCI */
 195 #define EHCI_DEV                0x12
 196 #define EHCI_FUNC               0
 197 #define EHCI_DEVID              0x7908
 198 #define EHCI1_DEVFN             PCI_DEVFN(EHCI_DEV, EHCI_FUNC)
 199 #define SOC_EHCI1_DEV           _SOC_DEV(EHCI_DEV, EHCI_FUNC)
 200
 201 /* SMBUS */
 202 #define SMBUS_DEV               0x14
 203 #define SMBUS_FUNC              0
 204 #define SMBUS_DEVID             0x790b
 205 #define SMBUS_DEVFN             PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
 206 #define SOC_SMBUS_DEV           _SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
 207
 208 /* LPC BUS */
 209 #define PCU_DEV                 0x14
 210 #define LPC_FUNC                3
 211 #define LPC_DEVID               0x790e
 212 #define LPC_DEVFN               PCI_DEVFN(PCU_DEV, LPC_FUNC)
 213 #define SOC_LPC_DEV             _SOC_DEV(PCU_DEV, LPC_FUNC)
 214
 215 /* SD Controller */
 216 #define SD_DEV                  0x14
 217 #define SD_FUNC                 7
 218 #define SD_DEVID                0x7906
 219 #define SD_DEVFN                PCI_DEVFN(SD_DEV, SD_FUNC)
 220 #define SOC_SD_DEV              _SOC_DEV(SD_DEV, SD_FUNC)
 221
 222 #endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */