src/soc/amd/stoneyridge/enable_usbdebug.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 // Use simple device model for this file even in ramstage
  16 #define __SIMPLE_DEVICE__
  17
  18 #include <stdint.h>
  19 #include <device/pci_ops.h>
  20 #include <device/pci_ehci.h>
  21 #include <device/pci_def.h>
  22 #include <soc/pci_devs.h>
  23 #include <soc/southbridge.h>
  24 #include <amdblocks/acpimmio.h>
  25
  26 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
  27 {
  28         pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS);
  29         return SOC_EHCI1_DEV;
  30 }
  31
  32 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
  33 {
  34         u32 reg32, value;
  35
  36         value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT;
  37         value |= DEBUG_PORT_ENABLE;
  38         reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);
  39         reg32 &= ~DEBUG_PORT_MASK;
  40         reg32 |= value;
  41         pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);
  42 }