src/soc/amd/picasso/cpu.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <cpu/cpu.h>
  16 #include <cpu/x86/mp.h>
  17 #include <cpu/x86/mtrr.h>
  18 #include <cpu/x86/msr.h>
  19 #include <cpu/x86/smm.h>
  20 #include <cpu/amd/msr.h>
  21 #include <cpu/amd/amd64_save_state.h>
  22 #include <cpu/x86/lapic.h>
  23 #include <device/device.h>
  24 #include <device/pci_ops.h>
  25 #include <soc/pci_devs.h>
  26 #include <soc/cpu.h>
  27 #include <soc/northbridge.h>
  28 #include <soc/smi.h>
  29 #include <soc/iomap.h>
  30 #include <console/console.h>
  31
  32 /*
  33  * MP and SMM loading initialization.
  34  */
  35 struct smm_relocation_params {
  36         msr_t tseg_base;
  37         msr_t tseg_mask;
  38 };
  39
  40 static struct smm_relocation_params smm_reloc_params;
  41
  42 /*
  43  * Do essential initialization tasks before APs can be fired up -
  44  *
  45  *  1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
  46  *  creates the MTRR solution that the APs will use. Otherwise APs will try to
  47  *  apply the incomplete solution as the BSP is calculating it.
  48  */
  49 static void pre_mp_init(void)
  50 {
  51         x86_setup_mtrrs_with_detect();
  52         x86_mtrr_check();
  53 }
  54
  55 int get_cpu_count(void)
  56 {
  57         return 1 + (cpuid_ecx(0x80000008) & 0xff);
  58 }
  59
  60 static void fill_in_relocation_params(struct smm_relocation_params *params)
  61 {
  62         uintptr_t tseg_base;
  63         size_t tseg_size;
  64
  65         smm_region(&tseg_base, &tseg_size);
  66
  67         params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB);
  68         params->tseg_base.hi = 0;
  69         params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB);
  70         params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1);
  71
  72         params->tseg_mask.lo |= SMM_TSEG_WB;
  73 }
  74
  75 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
  76                                 size_t *smm_save_state_size)
  77 {
  78         printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
  79
  80         fill_in_relocation_params(&smm_reloc_params);
  81
  82         smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
  83         *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
  84 }
  85
  86 static void relocation_handler(int cpu, uintptr_t curr_smbase,
  87                                 uintptr_t staggered_smbase)
  88 {
  89         struct smm_relocation_params *relo_params = &smm_reloc_params;
  90         amd64_smm_state_save_area_t *smm_state;
  91
  92         wrmsr(SMM_ADDR_MSR, relo_params->tseg_base);
  93         wrmsr(SMM_MASK_MSR, relo_params->tseg_mask);
  94
  95         smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase);
  96         smm_state->smbase = staggered_smbase;
  97 }
  98
  99 static const struct mp_ops mp_ops = {
 100         .pre_mp_init = pre_mp_init,
 101         .get_cpu_count = get_cpu_count,
 102         .get_smm_info = get_smm_info,
 103         .relocation_handler = relocation_handler,
 104         .post_mp_init = enable_smi_generation,
 105 };
 106
 107 void picasso_init_cpus(struct device *dev)
 108 {
 109         /* Clear for take-off */
 110         if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
 111                 printk(BIOS_ERR, "MP initialization failure.\n");
 112
 113         /* The flash is now no longer cacheable. Reset to WP for performance. */
 114         mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
 115
 116         set_warm_reset_flag();
 117 }
 118
 119 static void model_17_init(struct device *dev)
 120 {
 121         check_mca();
 122         setup_lapic();
 123 }
 124
 125 static struct device_operations cpu_dev_ops = {
 126         .init = model_17_init,
 127 };
 128
 129 static struct cpu_device_id cpu_table[] = {
 130         { X86_VENDOR_AMD, 0x810f80 },
 131         { X86_VENDOR_AMD, 0x810f81 },
 132         { 0, 0 },
 133 };
 134
 135 static const struct cpu_driver model_17 __cpu_driver = {
 136         .ops      = &cpu_dev_ops,
 137         .id_table = cpu_table,
 138 };