src/soc/amd/picasso/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 /*
  16  * ACPI - create the Fixed ACPI Description Tables (FADT)
  17  */
  18
  19 #include <string.h>
  20 #include <console/console.h>
  21 #include <arch/acpi.h>
  22 #include <arch/acpigen.h>
  23 #include <device/pci_ops.h>
  24 #include <arch/ioapic.h>
  25 #include <cpu/x86/smm.h>
  26 #include <cbmem.h>
  27 #include <device/device.h>
  28 #include <device/pci.h>
  29 #include <amdblocks/acpimmio.h>
  30 #include <amdblocks/acpi.h>
  31 #include <soc/acpi.h>
  32 #include <soc/pci_devs.h>
  33 #include <soc/cpu.h>
  34 #include <soc/southbridge.h>
  35 #include <soc/northbridge.h>
  36 #include <soc/nvs.h>
  37 #include <soc/gpio.h>
  38 #include <version.h>
  39
  40 unsigned long acpi_fill_madt(unsigned long current)
  41 {
  42         /* create all subtables for processors */
  43         current = acpi_create_madt_lapics(current);
  44
  45         /* Write Kern IOAPIC, only one */
  46         current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
  47                         CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
  48
  49         /* 0: mean bus 0--->ISA */
  50         /* 0: PIC 0 */
  51         /* 2: APIC 2 */
  52         /* 5 mean: 0101 --> Edge-triggered, Active high */
  53         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  54                                                 current, 0, 0, 2, 0);
  55         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  56                                                 current, 0, 9, 9, 0xf);
  57
  58         /* create all subtables for processors */
  59         current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
  60                         0xff, 5, 1);
  61         /* 1: LINT1 connect to NMI */
  62
  63         return current;
  64 }
  65
  66 /*
  67  * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
  68  * in the ACPI 3.0b specification.
  69  */
  70 void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
  71 {
  72         acpi_header_t *header = &(fadt->header);
  73
  74         printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE);
  75
  76         /* Prepare the header */
  77         memset((void *)fadt, 0, sizeof(acpi_fadt_t));
  78         memcpy(header->signature, "FACP", 4);
  79         header->length = sizeof(acpi_fadt_t);
  80         header->revision = get_acpi_table_revision(FADT);
  81         memcpy(header->oem_id, OEM_ID, 6);
  82         memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
  83         memcpy(header->asl_compiler_id, ASLC, 4);
  84         header->asl_compiler_revision = asl_revision;
  85
  86         fadt->firmware_ctrl = (u32) facs;
  87         fadt->dsdt = (u32) dsdt;
  88         fadt->reserved = 0;             /* reserved, should be 0 ACPI 3.0 */
  89         fadt->preferred_pm_profile = FADT_PM_PROFILE;
  90         fadt->sci_int = 9;              /* IRQ 09 - ACPI SCI */
  91
  92         if (CONFIG(HAVE_SMI_HANDLER)) {
  93                 fadt->smi_cmd = APM_CNT;
  94                 fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
  95                 fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
  96                 fadt->s4bios_req = 0;   /* Not supported */
  97                 fadt->pstate_cnt = 0;   /* Not supported */
  98                 fadt->cst_cnt = 0;      /* Not supported */
  99         } else {
 100                 fadt->smi_cmd = 0;      /* disable system management mode */
 101                 fadt->acpi_enable = 0;  /* unused if SMI_CMD = 0 */
 102                 fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */
 103                 fadt->s4bios_req = 0;   /* unused if SMI_CMD = 0 */
 104                 fadt->pstate_cnt = 0;   /* unused if SMI_CMD = 0 */
 105                 fadt->cst_cnt = 0x00;   /* unused if SMI_CMD = 0 */
 106         }
 107
 108         fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
 109         fadt->pm1b_evt_blk = 0x0000;
 110         fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
 111         fadt->pm1b_cnt_blk = 0x0000;
 112         fadt->pm2_cnt_blk = 0x0000;
 113         fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
 114         fadt->gpe0_blk = ACPI_GPE0_BLK;
 115         fadt->gpe1_blk = 0x0000;                /* No gpe1 block  */
 116
 117         fadt->pm1_evt_len = 4;  /* 32 bits */
 118         fadt->pm1_cnt_len = 2;  /* 16 bits */
 119         fadt->pm2_cnt_len = 0;
 120         fadt->pm_tmr_len = 4;   /* 32 bits */
 121         fadt->gpe0_blk_len = 8; /* 64 bits */
 122         fadt->gpe1_blk_len = 0;
 123         fadt->gpe1_base = 0;
 124
 125         fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 126         fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 127         fadt->flush_size = 0;   /* set to 0 if WBINVD is 1 in flags */
 128         fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
 129         fadt->duty_offset = 1;  /* CLK_VAL bits 3:1 */
 130         fadt->duty_width = 3;   /* CLK_VAL bits 3:1 */
 131         fadt->day_alrm = 0;     /* 0x7d these have to be */
 132         fadt->mon_alrm = 0;     /* 0x7e added to cmos.layout */
 133         fadt->century = 0;      /* 0x7f to make rtc alarm work */
 134         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
 135         fadt->res2 = 0;         /* reserved, MUST be 0 ACPI 3.0 */
 136         fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
 137                                 ACPI_FADT_C1_SUPPORTED |
 138                                 ACPI_FADT_SLEEP_BUTTON |
 139                                 ACPI_FADT_S4_RTC_WAKE |
 140                                 ACPI_FADT_32BIT_TIMER |
 141                                 ACPI_FADT_RESET_REGISTER |
 142                                 ACPI_FADT_PCI_EXPRESS_WAKE |
 143                                 ACPI_FADT_PLATFORM_CLOCK |
 144                                 ACPI_FADT_S4_RTC_VALID |
 145                                 ACPI_FADT_REMOTE_POWER_ON;
 146
 147         /* Format is from 5.2.3.1: Generic Address Structure */
 148         /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
 149         /* 8 bit write of value 0x06 to 0xCF9 in IO space */
 150         fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
 151         fadt->reset_reg.bit_width = 8;
 152         fadt->reset_reg.bit_offset = 0;
 153         fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 154         fadt->reset_reg.addrl = SYS_RESET;
 155         fadt->reset_reg.addrh = 0x0;
 156
 157         fadt->reset_value = 6;
 158
 159         fadt->ARM_boot_arch = 0;        /* MUST be 0 ACPI 3.0 */
 160         fadt->FADT_MinorVersion = 0;    /* MUST be 0 ACPI 3.0 */
 161
 162         fadt->x_firmware_ctl_l = 0;     /* set to 0 if firmware_ctrl is used */
 163         fadt->x_firmware_ctl_h = 0;
 164         fadt->x_dsdt_l = (u32) dsdt;
 165         fadt->x_dsdt_h = 0;
 166
 167         fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 168         fadt->x_pm1a_evt_blk.bit_width = 32;
 169         fadt->x_pm1a_evt_blk.bit_offset = 0;
 170         fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
 171         fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
 172         fadt->x_pm1a_evt_blk.addrh = 0x0;
 173
 174         fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 175         fadt->x_pm1b_evt_blk.bit_width = 0;
 176         fadt->x_pm1b_evt_blk.bit_offset = 0;
 177         fadt->x_pm1b_evt_blk.access_size = 0;
 178         fadt->x_pm1b_evt_blk.addrl = 0x0;
 179         fadt->x_pm1b_evt_blk.addrh = 0x0;
 180
 181
 182         fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 183         fadt->x_pm1a_cnt_blk.bit_width = 16;
 184         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 185         fadt->x_pm1a_cnt_blk.access_size = 0;
 186         fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
 187         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 188
 189         fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 190         fadt->x_pm1b_cnt_blk.bit_width = 0;
 191         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 192         fadt->x_pm1b_cnt_blk.access_size = 0;
 193         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 194         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 195
 196         /*
 197          * Note: Under this current AMD C state implementation, this is no
 198          *       longer used and should not be reported to OS.
 199          */
 200         fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 201         fadt->x_pm2_cnt_blk.bit_width = 0;
 202         fadt->x_pm2_cnt_blk.bit_offset = 0;
 203         fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 204         fadt->x_pm2_cnt_blk.addrl = 0;
 205         fadt->x_pm2_cnt_blk.addrh = 0x0;
 206
 207
 208         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 209         fadt->x_pm_tmr_blk.bit_width = 32;
 210         fadt->x_pm_tmr_blk.bit_offset = 0;
 211         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 212         fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
 213         fadt->x_pm_tmr_blk.addrh = 0x0;
 214
 215
 216         fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 217         fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
 218         fadt->x_gpe0_blk.bit_offset = 0;
 219         fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 220         fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
 221         fadt->x_gpe0_blk.addrh = 0x0;
 222
 223
 224         fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 225         fadt->x_gpe1_blk.bit_width = 0;
 226         fadt->x_gpe1_blk.bit_offset = 0;
 227         fadt->x_gpe1_blk.access_size = 0;
 228         fadt->x_gpe1_blk.addrl = 0;
 229         fadt->x_gpe1_blk.addrh = 0x0;
 230
 231         header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
 232 }
 233
 234 void generate_cpu_entries(struct device *device)
 235 {
 236         int cores, cpu;
 237
 238         cores = get_cpu_count();
 239         printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
 240
 241         /* Generate BSP \_PR.P000 */
 242         acpigen_write_processor(0, ACPI_GPE0_BLK, 6);
 243         acpigen_pop_len();
 244
 245         /* Generate AP \_PR.Pxxx */
 246         for (cpu = 1; cpu < cores; cpu++) {
 247                 acpigen_write_processor(cpu, 0, 0);
 248                 acpigen_pop_len();
 249         }
 250 }
 251
 252 unsigned long southbridge_write_acpi_tables(struct device *device,
 253                 unsigned long current,
 254                 struct acpi_rsdp *rsdp)
 255 {
 256         return acpi_write_hpet(device, current, rsdp);
 257 }
 258
 259 static void acpi_create_gnvs(struct global_nvs_t *gnvs)
 260 {
 261         /* Clear out GNVS. */
 262         memset(gnvs, 0, sizeof(*gnvs));
 263
 264         if (CONFIG(CONSOLE_CBMEM))
 265                 gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
 266
 267         if (CONFIG(CHROMEOS)) {
 268                 /* Initialize Verified Boot data */
 269                 chromeos_init_chromeos_acpi(&gnvs->chromeos);
 270                 gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
 271         }
 272
 273         /* Set unknown wake source */
 274         gnvs->pm1i = ~0ULL;
 275         gnvs->gpei = ~0ULL;
 276
 277         /* CPU core count */
 278         gnvs->pcnt = dev_count_cpu();
 279 }
 280
 281 void southbridge_inject_dsdt(struct device *device)
 282 {
 283         struct global_nvs_t *gnvs;
 284
 285         gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 286
 287         if (gnvs) {
 288                 acpi_create_gnvs(gnvs);
 289
 290                 /* Add it to DSDT */
 291                 acpigen_write_scope("\\");
 292                 acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
 293                 acpigen_pop_len();
 294         }
 295 }
 296
 297 static void acpigen_soc_get_gpio_in_local5(uintptr_t addr)
 298 {
 299         /*
 300          *   Store (\_SB.GPR2 (addr), Local5)
 301          * \_SB.GPR2 is used to read control byte 2 from control register.
 302          * / It is defined in gpio_lib.asl.
 303          */
 304         acpigen_write_store();
 305         acpigen_emit_namestring("\\_SB.GPR2");
 306         acpigen_write_integer(addr);
 307         acpigen_emit_byte(LOCAL5_OP);
 308 }
 309
 310 static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
 311 {
 312         if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
 313                 printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
 314                                         " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 315                 return -1;
 316         }
 317         uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
 318
 319         acpigen_soc_get_gpio_in_local5(addr);
 320
 321         /* If (And (Local5, mask)) */
 322         acpigen_write_if_and(LOCAL5_OP, mask);
 323
 324         /* Store (One, Local0) */
 325         acpigen_write_store_ops(ONE_OP, LOCAL0_OP);
 326
 327         acpigen_pop_len();      /* If */
 328
 329         /* Else */
 330         acpigen_write_else();
 331
 332         /* Store (Zero, Local0) */
 333         acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);
 334
 335         acpigen_pop_len();      /* Else */
 336
 337         return 0;
 338 }
 339
 340 static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
 341 {
 342         if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
 343                 printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
 344                                         " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
 345                 return -1;
 346         }
 347         uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
 348
 349         /* Store (0x40, Local0) */
 350         acpigen_write_store();
 351         acpigen_write_integer(GPIO_PIN_OUT);
 352         acpigen_emit_byte(LOCAL0_OP);
 353
 354         acpigen_soc_get_gpio_in_local5(addr);
 355
 356         if (val) {
 357                 /* Or (Local5, GPIO_PIN_OUT, Local5) */
 358                 acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP);
 359         } else {
 360                 /* Not (GPIO_PIN_OUT, Local6) */
 361                 acpigen_write_not(LOCAL0_OP, LOCAL6_OP);
 362
 363                 /* And (Local5, Local6, Local5) */
 364                 acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);
 365         }
 366
 367         /*
 368          *   SB.GPW2 (addr, Local5)
 369          * \_SB.GPW2 is used to write control byte in control register
 370          * / byte 2. It is defined in gpio_lib.asl.
 371          */
 372         acpigen_emit_namestring("\\_SB.GPW2");
 373         acpigen_write_integer(addr);
 374         acpigen_emit_byte(LOCAL5_OP);
 375
 376         return 0;
 377 }
 378
 379 int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
 380 {
 381         return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN);
 382 }
 383
 384 int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
 385 {
 386         return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT);
 387 }
 388
 389 int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
 390 {
 391         return acpigen_soc_set_gpio_val(gpio_num, 1);
 392 }
 393
 394 int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 395 {
 396         return acpigen_soc_set_gpio_val(gpio_num, 0);
 397 }