src/soc/amd/common/block/lpc/lpc_util.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <stdint.h>
  16 #include <device/device.h>
  17 #include <device/pci_ops.h>
  18 #include <device/pci_def.h>
  19 #include <amdblocks/lpc.h>
  20 #include <soc/iomap.h>
  21 #include <soc/southbridge.h>
  22
  23 /* The LPC-ISA bridge is always at D14F3 */
  24 #if !defined(__SIMPLE_DEVICE__)
  25 #include <device/device.h>
  26 #define _LPCB_DEV pcidev_on_root(0x14, 0x3)
  27 #else
  28 #define _LPCB_DEV PCI_DEV(0, 0x14, 0x3)
  29 #endif
  30
  31 /*
  32  * Structure to simplify code obtaining the total of used wide IO
  33  * registers and the size assigned to each.
  34  */
  35 static const struct wide_io_ioport_and_bits {
  36         uint32_t enable;
  37         uint16_t port;
  38         uint8_t alt;
  39 } wio_io_en[] = {
  40         {
  41                 .enable = LPC_WIDEIO0_ENABLE,
  42                 .port = LPC_WIDEIO_GENERIC_PORT,
  43                 .alt = LPC_ALT_WIDEIO0_ENABLE
  44         },
  45         {
  46                 .enable = LPC_WIDEIO1_ENABLE,
  47                 .port = LPC_WIDEIO1_GENERIC_PORT,
  48                 .alt = LPC_ALT_WIDEIO1_ENABLE
  49         },
  50         {
  51                 .enable = LPC_WIDEIO2_ENABLE,
  52                 .port = LPC_WIDEIO2_GENERIC_PORT,
  53                 .alt = LPC_ALT_WIDEIO2_ENABLE
  54         }
  55 };
  56
  57 /**
  58  * @brief Find the size of a particular wide IO
  59  *
  60  * @param index = index of desired wide IO
  61  *
  62  * @return size of desired wide IO
  63  */
  64 uint16_t lpc_wideio_size(int index)
  65 {
  66         uint32_t enable_register;
  67         uint16_t size = 0;
  68         uint8_t alternate_register;
  69
  70         if (index >= ARRAY_SIZE(wio_io_en))
  71                 return size;
  72         enable_register = pci_read_config32(_LPCB_DEV,
  73                                 LPC_IO_OR_MEM_DECODE_ENABLE);
  74         alternate_register = pci_read_config8(_LPCB_DEV,
  75                                 LPC_ALT_WIDEIO_RANGE_ENABLE);
  76         if (enable_register & wio_io_en[index].enable)
  77                 size = (alternate_register & wio_io_en[index].alt) ?
  78                                 16 : 512;
  79         return size;
  80 }
  81
  82 /**
  83  * @brief Identify if any LPC wide IO is covering the IO range
  84  *
  85  * @param start = start of IO range
  86  * @param size = size of IO range
  87  *
  88  * @return Index of wide IO covering the range or error
  89  */
  90 int lpc_find_wideio_range(uint16_t start, uint16_t size)
  91 {
  92         int i, index = WIDEIO_RANGE_ERROR;
  93         uint16_t end, current_size, start_wideio, end_wideio;
  94
  95         end = start + size;
  96         for (i = 0; i < ARRAY_SIZE(wio_io_en); i++) {
  97                 current_size = lpc_wideio_size(i);
  98                 if (current_size == 0)
  99                         continue;
 100                 start_wideio = pci_read_config16(_LPCB_DEV,
 101                                                  wio_io_en[i].port);
 102                 end_wideio = start_wideio + current_size;
 103                 if ((start >= start_wideio) && (end <= end_wideio)) {
 104                         index = i;
 105                         break;
 106                 }
 107         }
 108         return index;
 109 }
 110
 111 /**
 112  * @brief Program a LPC wide IO to support an IO range
 113  *
 114  * @param start = start of range to be routed through wide IO
 115  * @param size = size of range to be routed through wide IO
 116  *
 117  * @return Index of wide IO register used or error
 118  */
 119 int lpc_set_wideio_range(uint16_t start, uint16_t size)
 120 {
 121         int i, index = WIDEIO_RANGE_ERROR;
 122         uint32_t enable_register;
 123         uint8_t alternate_register;
 124
 125         enable_register = pci_read_config32(_LPCB_DEV,
 126                                            LPC_IO_OR_MEM_DECODE_ENABLE);
 127         alternate_register = pci_read_config8(_LPCB_DEV,
 128                                               LPC_ALT_WIDEIO_RANGE_ENABLE);
 129         for (i = 0; i < ARRAY_SIZE(wio_io_en); i++) {
 130                 if (enable_register & wio_io_en[i].enable)
 131                         continue;
 132                 index = i;
 133                 pci_write_config16(_LPCB_DEV, wio_io_en[i].port, start);
 134                 enable_register |= wio_io_en[i].enable;
 135                 pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE,
 136                                    enable_register);
 137                 if (size <= 16)
 138                         alternate_register |= wio_io_en[i].alt;
 139                 else
 140                         alternate_register &= ~wio_io_en[i].alt;
 141                 pci_write_config8(_LPCB_DEV,
 142                                   LPC_ALT_WIDEIO_RANGE_ENABLE,
 143                                   alternate_register);
 144                 break;
 145         }
 146         return index;
 147 }
 148
 149 void lpc_enable_port80(void)
 150 {
 151         u8 byte;
 152
 153         byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
 154         byte |= DECODE_IO_PORT_ENABLE4_H;
 155         pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
 156 }
 157
 158 void lpc_enable_pci_port80(void)
 159 {
 160         u8 byte;
 161
 162         byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
 163         byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */
 164         pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
 165 }
 166
 167 void lpc_enable_sio_decode(const bool addr)
 168 {
 169         uint32_t decodes;
 170         uint32_t enable;
 171
 172         decodes = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
 173         enable = addr == LPC_SELECT_SIO_2E2F ?
 174                         DECODE_SIO_ENABLE : DECODE_ALTERNATE_SIO_ENABLE;
 175         decodes |= enable;
 176         pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, decodes);
 177 }
 178
 179 void lpc_enable_decode(uint32_t decodes)
 180 {
 181         pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes);
 182 }
 183
 184 /*
 185  * Clear all decoding to the LPC bus and erase any range registers associated
 186  * with the enable bits.
 187  */
 188 void lpc_disable_decodes(void)
 189 {
 190         uint32_t reg;
 191
 192         lpc_enable_decode(0);
 193         reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
 194         reg &= LPC_SYNC_TIMEOUT_COUNT_MASK | LPC_SYNC_TIMEOUT_COUNT_ENABLE;
 195         pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg);
 196
 197         /* D14F3x48 enables ranges configured in additional registers */
 198         pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0);
 199         pci_write_config32(_LPCB_DEV, LPC_MEM_PORT0, 0);
 200         pci_write_config32(_LPCB_DEV, LPC_WIDEIO2_GENERIC_PORT, 0);
 201 }
 202
 203 uintptr_t lpc_spibase(void)
 204 {
 205         u32 base, enables;
 206
 207         /* Make sure the base address is predictable */
 208         base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
 209         enables = base & SPI_PRESERVE_BITS;
 210         base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);
 211
 212         if (!base) {
 213                 base = SPI_BASE_ADDRESS;
 214                 pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER,
 215                                         base | enables | SPI_ROM_ENABLE);
 216                 /* PCI_COMMAND_MEMORY is read-only and enabled. */
 217         }
 218         return base;
 219 }
 220
 221 /*
 222  * Enable FCH to decode TPM associated Memory and IO regions
 223  *
 224  * Enable decoding of TPM cycles defined in TPM 1.2 spec
 225  * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
 226  * 0x7e and 0xef-0xee.
 227  * This function should be called if TPM is connected in any way to the FCH and
 228  * conforms to the regions decoded.
 229  * Absent any other routing configuration the TPM cycles will be claimed by the
 230  * LPC bus
 231  */
 232 void lpc_tpm_decode(void)
 233 {
 234         u32 value;
 235
 236         value = pci_read_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE);
 237         value |= TPM_12_EN | TPM_LEGACY_EN;
 238         pci_write_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
 239 }
 240
 241 /*
 242  * Enable FCH to decode TPM associated Memory and IO regions to SPI
 243  *
 244  * This should be used if TPM is connected to SPI bus.
 245  * Assumes SPI address space is already configured via a call to lpc_spibase().
 246  */
 247 void lpc_tpm_decode_spi(void)
 248 {
 249         /* Enable TPM decoding to FCH */
 250         lpc_tpm_decode();
 251
 252         /* Route TPM accesses to SPI */
 253         u32 spibase = pci_read_config32(_LPCB_DEV,
 254                                         SPIROM_BASE_ADDRESS_REGISTER);
 255         pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase
 256                                         | ROUTE_TPM_2_SPI);
 257 }
 258
 259 /*
 260  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
 261  *
 262  * Hardware should enable LPC ROM by pin straps. This function does not
 263  * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
 264  *
 265  * The southbridge power-on default is to map 512K ROM space.
 266  *
 267  */
 268 void lpc_enable_rom(void)
 269 {
 270         u8 reg8;
 271
 272         /*
 273          * Decode variable LPC ROM address ranges 1 and 2.
 274          * Bits 3-4 are not defined in any publicly available datasheet
 275          */
 276         reg8 = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
 277         reg8 |= (1 << 3) | (1 << 4);
 278         pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8);
 279
 280         /*
 281          * LPC ROM address range 1:
 282          * Enable LPC ROM range mirroring start at 0x000e(0000).
 283          */
 284         pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE1_START, 0x000e);
 285
 286         /* Enable LPC ROM range mirroring end at 0x000f(ffff). */
 287         pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE1_END, 0x000f);
 288
 289         /*
 290          * LPC ROM address range 2:
 291          *
 292          * Enable LPC ROM range start at:
 293          * 0xfff8(0000): 512KB
 294          * 0xfff0(0000): 1MB
 295          * 0xffe0(0000): 2MB
 296          * 0xffc0(0000): 4MB
 297          */
 298         pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
 299                                         - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
 300
 301         /* Enable LPC ROM range end at 0xffff(ffff). */
 302         pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
 303 }
 304
 305 void lpc_enable_spi_prefetch(void)
 306 {
 307         uint32_t dword;
 308
 309         dword = pci_read_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL);
 310         dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN;
 311         pci_write_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
 312 }
 313
 314 uintptr_t lpc_get_spibase(void)
 315 {
 316         u32 base;
 317
 318         base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
 319         base = ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
 320         return (uintptr_t)base;
 321 }
 322
 323 void lpc_set_spibase(u32 base, u32 enable)
 324 {
 325         u32 reg32;
 326
 327         /* only two types of CS# enables are allowed */
 328         enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE;
 329
 330         reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
 331
 332         reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
 333         reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE);
 334         reg32 |= enable;
 335         reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
 336
 337         pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
 338 }