src/soc/amd/common/block/include/amdblocks/psp.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef __AMD_PSP_H__
  16 #define __AMD_PSP_H__
  17
  18 #include <amdblocks/agesawrapper.h>
  19 #include <soc/pci_devs.h>
  20 #include <types.h>
  21
  22 /* Extra, Special Purpose Registers in the PSP PCI Config Space */
  23
  24 /* PSP Mirror Features Capabilities and Control Register */
  25 #define PSP_PCI_MIRRORCTRL1_REG       0x44    /* PSP Mirror Ctrl Reg          */
  26 #define   PMNXTPTRW_MASK              0xff    /* PCI AFCR pointer mask        */
  27 #define   PMNXTPTRW_EXPOSE            0xa4    /* Pointer to expose the AFCR   */
  28
  29 #define PSP_PCI_EXT_HDR_CTRL          0x48    /* Extra PCI Header Ctrl        */
  30 #define   MAGIC_ENABLES               0x34    /* Extra PCI HDR Ctl Enables    */
  31
  32 #define PSP_MAILBOX_BASE              0x70    /* Mailbox offset from PCIe BAR */
  33
  34 #define MSR_CU_CBBCFG                 0xc00110a2 /* PSP Pvt Blk Base Addr */
  35 #define   BAR3HIDE                    BIT(12) /* Bit to hide BAR3 addr */
  36
  37 /* x86 to PSP commands */
  38 #define MBOX_BIOS_CMD_DRAM_INFO    0x01
  39 #define MBOX_BIOS_CMD_SMM_INFO     0x02
  40 #define MBOX_BIOS_CMD_SX_INFO      0x03
  41 #define MBOX_BIOS_CMD_RSM_INFO     0x04
  42 #define MBOX_BIOS_CMD_PSP_QUERY    0x05
  43 #define MBOX_BIOS_CMD_BOOT_DONE    0x06
  44 #define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07
  45 #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08
  46 #define MBOX_BIOS_CMD_NOP          0x09
  47 #define MBOX_BIOS_CMD_SMU_FW       0x19
  48 #define MBOX_BIOS_CMD_SMU_FW2      0x1a
  49 #define MBOX_BIOS_CMD_ABORT        0xfe
  50
  51 /* generic PSP interface status */
  52 #define STATUS_INITIALIZED         0x1
  53 #define STATUS_ERROR               0x2
  54 #define STATUS_TERMINATED          0x4
  55 #define STATUS_HALT                0x8
  56 #define STATUS_RECOVERY            0x10
  57
  58 /* psp_mbox consists of hardware registers beginning at PSPx000070
  59  *   mbox_command: BIOS->PSP command, cleared by PSP when complete
  60  *   mbox_status:  BIOS->PSP interface status
  61  *   cmd_response: pointer to command/response buffer
  62  */
  63 struct psp_mbox {
  64         u32 mbox_command;
  65         u32 mbox_status;
  66         u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */
  67 } __packed;
  68
  69 /* command/response format, BIOS builds this in memory
  70  *   mbox_buffer_header: generic header
  71  *   mbox_buffer:        command-specific buffer format
  72  *
  73  * AMD reference code aligns and pads all buffers to 32 bytes.
  74  */
  75 struct mbox_buffer_header {
  76         u32 size;       /* total size of buffer */
  77         u32 status;     /* command status, filled by PSP if applicable */
  78 } __packed;
  79
  80 /*
  81  * command-specific buffer definitions:  see NDA document #54267
  82  * The following commands need a buffer definition if they are to be used.
  83  * All other commands will work with the default buffer.
  84  * MBOX_BIOS_CMD_SMM_INFO               MBOX_BIOS_CMD_PSP_QUERY
  85  * MBOX_BIOS_CMD_SX_INFO                MBOX_BIOS_CMD_S3_DATA_INFO
  86  * MBOX_BIOS_CMD_RSM_INFO
  87  */
  88
  89 struct mbox_default_buffer {    /* command-response buffer unused by command */
  90         struct mbox_buffer_header header;
  91 } __attribute__((packed, aligned(32)));
  92
  93 /* send_psp_command() error codes */
  94 #define PSPSTS_SUCCESS      0
  95 #define PSPSTS_NOBASE       1
  96 #define PSPSTS_HALTED       2
  97 #define PSPSTS_RECOVERY     3
  98 #define PSPSTS_SEND_ERROR   4
  99 #define PSPSTS_INIT_TIMEOUT 5
 100 #define PSPSTS_CMD_TIMEOUT  6
 101 /* other error codes */
 102 #define PSPSTS_UNSUPPORTED  7
 103 #define PSPSTS_INVALID_NAME 8
 104 #define PSPSTS_INVALID_BLOB 9
 105
 106 #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */
 107 #define PSP_CMD_TIMEOUT 1000 /* 1 second */
 108
 109 /* BIOS-to-PSP functions return 0 if successful, else negative value */
 110
 111 int psp_notify_dram(void);
 112
 113 /*
 114  * type: identical to the corresponding PSP command, e.g. pass
 115  *       MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob.
 116  * name: cbfs file name
 117  */
 118 int psp_load_named_blob(int type, const char *name);
 119
 120 #endif /* __AMD_PSP_H__ */