2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
38 config COMMON_CBFS_SPI_WRAPPER
44 Use common wrapper to interface CBFS to SPI bootrom.
46 config MULTIPLE_CBFS_INSTANCES
47 bool "Multiple CBFS instances in the bootrom"
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
56 prompt "Compiler to use"
59 This option allows you to select the compiler used for building
61 You must build the coreboot crosscompiler for the board that you
64 To build all the GCC crosscompilers (takes a LONG time), run:
67 For help on individual architectures, run the command:
73 Use the GNU Compiler Collection (GCC) to build coreboot.
75 For details see http://gcc.gnu.org.
77 config COMPILER_LLVM_CLANG
78 bool "LLVM/clang (TESTING ONLY - Not currently working)"
80 Use LLVM/clang to build coreboot. To use this, you must build the
81 coreboot version of the clang compiler. Run the command
83 Note that this option is not currently working correctly and should
84 really only be selected if you're trying to work on getting clang
87 For details see http://clang.llvm.org.
92 bool "Allow building with any toolchain"
94 depends on COMPILER_GCC
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
102 bool "Use ccache to speed up (re)compilation"
105 Enables the use of ccache for faster builds.
107 Requires the ccache utility in your system $PATH.
109 For details see https://ccache.samba.org.
112 bool "Generate flashmap descriptor parser using flex and bison"
115 Enable this option if you are working on the flashmap descriptor
116 parser and made changes to fmd_scanner.l or fmd_parser.y.
118 Otherwise, say N to use the provided pregenerated scanner/parser.
120 config SCONFIG_GENPARSER
121 bool "Generate SCONFIG parser using flex and bison"
124 Enable this option if you are working on the sconfig device tree
125 parser and made changes to sconfig.l or sconfig.y.
127 Otherwise, say N to use the provided pregenerated scanner/parser.
129 config USE_OPTION_TABLE
130 bool "Use CMOS for configuration values"
132 depends on HAVE_OPTION_TABLE
134 Enable this option if coreboot shall read options from the "CMOS"
135 NVRAM instead of using hard-coded values.
137 config STATIC_OPTION_TABLE
138 bool "Load default configuration values into CMOS on each boot"
140 depends on USE_OPTION_TABLE
142 Enable this option to reset "CMOS" NVRAM values to default on
143 every boot. Use this if you want the NVRAM configuration to
144 never be modified from its default values.
146 config UNCOMPRESSED_RAMSTAGE
150 config COMPRESS_RAMSTAGE
151 bool "Compress ramstage with LZMA"
152 default y if !UNCOMPRESSED_RAMSTAGE
155 Compress ramstage to save memory in the flash image. Note
156 that decompression might slow down booting if the boot flash
157 is connected through a slow link (i.e. SPI).
159 config COMPRESS_PRERAM_STAGES
160 bool "Compress romstage and verstage with LZ4"
164 Compress romstage and (if it exists) verstage with LZ4 to save flash
165 space and speed up boot, since the time for reading the image from SPI
166 (and in the vboot case verifying it) is usually much greater than the
167 time spent decompressing. Doesn't work for XIP stages (assume all
168 ARCH_X86 for now) for obvious reasons.
170 config INCLUDE_CONFIG_FILE
171 bool "Include the coreboot .config file into the ROM image"
174 Include the .config file that was used to compile coreboot
175 in the (CBFS) ROM image. This is useful if you want to know which
176 options were used to build a specific coreboot.rom image.
178 Saying Y here will increase the image size by 2-3KB.
180 You can use the following command to easily list the options:
182 grep -a CONFIG_ coreboot.rom
184 Alternatively, you can also use cbfstool to print the image
185 contents (including the raw 'config' item we're looking for).
189 $ cbfstool coreboot.rom print
190 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
194 Name Offset Type Size
195 cmos_layout.bin 0x0 cmos layout 1159
196 fallback/romstage 0x4c0 stage 339756
197 fallback/ramstage 0x53440 stage 186664
198 fallback/payload 0x80dc0 payload 51526
199 config 0x8d740 raw 3324
200 (empty) 0x8e480 null 3610440
202 config EARLY_CBMEM_INIT
203 def_bool !LATE_CBMEM_INIT
205 config COLLECT_TIMESTAMPS
206 bool "Create a table of timestamps collected during boot"
209 Make coreboot create a table of timer-ID/timer-value pairs to
210 allow measuring time spent at different phases of the boot process.
213 bool "Allow use of binary-only repository"
216 This draws in the blobs repository, which contains binary files that
217 might be required for some chipsets or boards.
218 This flag ensures that a "Free" option remains available for users.
221 bool "Code coverage support"
222 depends on COMPILER_GCC
225 Add code coverage support for coreboot. This will store code
226 coverage information in CBMEM for extraction from user space.
229 config RELOCATABLE_MODULES
233 If RELOCATABLE_MODULES is selected then support is enabled for
234 building relocatable modules in the RAM stage. Those modules can be
235 loaded anywhere and all the relocations are handled automatically.
237 config RELOCATABLE_RAMSTAGE
238 depends on EARLY_CBMEM_INIT
239 bool "Build the ramstage to be relocatable in 32-bit address space."
241 select RELOCATABLE_MODULES
243 The reloctable ramstage support allows for the ramstage to be built
244 as a relocatable module. The stage loader can identify a place
245 out of the OS way so that copying memory is unnecessary during an S3
246 wake. When selecting this option the romstage is responsible for
247 determing a stack location to use for loading the ramstage.
249 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
250 depends on RELOCATABLE_RAMSTAGE
251 bool "Cache the relocated ramstage outside of cbmem."
254 The relocated ramstage is saved in an area specified by the
255 by the board and/or chipset.
257 config FLASHMAP_OFFSET
258 hex "Flash Map Offset"
259 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
260 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
261 default CBFS_SIZE if !ARCH_X86
264 Offset of flash map in firmware image
266 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
268 prompt "Bootblock behaviour"
269 default BOOTBLOCK_SIMPLE
271 config BOOTBLOCK_SIMPLE
272 bool "Always load fallback"
274 config BOOTBLOCK_NORMAL
275 bool "Switch to normal if CMOS says so"
279 # To be selected by arch, SoC or mainboard if it does not want use the normal
280 # src/lib/bootblock.c#main() C entry point.
281 config BOOTBLOCK_CUSTOM
285 config BOOTBLOCK_SOURCE
287 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
288 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
290 # To be selected by arch or platform if a C environment is available during the
291 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
292 config C_ENVIRONMENT_BOOTBLOCK
296 config SKIP_MAX_REBOOT_CNT_CLEAR
297 bool "Do not clear reboot count after successful boot"
299 depends on BOOTBLOCK_NORMAL
301 Do not clear the reboot count immediately after successful boot.
302 Set to allow the payload to control normal/fallback image recovery.
303 Note that it is the responsibility of the payload to reset the
304 normal boot bit to 1 after each successsful boot.
307 bool "Update existing coreboot.rom image"
310 If this option is enabled, no new coreboot.rom file
311 is created. Instead it is expected that there already
312 is a suitable file for further processing.
313 The bootblock will not be modified.
315 If unsure, select 'N'
317 config GENERIC_GPIO_LIB
321 If enabled, compile the generic GPIO library. A "generic" GPIO
322 implies configurability usually found on SoCs, particularly the
323 ability to control internal pull resistors.
329 Mainboards that can read a board ID from the hardware straps
330 (ie. GPIO) select this configuration option.
332 config BOARD_ID_MANUAL
335 depends on !BOARD_ID_AUTO
337 If you want to maintain a board ID, but the hardware does not
338 have straps to automatically determine the ID, you can say Y
339 here and add a file named 'board_id' to CBFS. If you don't know
340 what this is about, say N.
342 config BOARD_ID_STRING
345 depends on BOARD_ID_MANUAL
347 This string is placed in the 'board_id' CBFS file for indicating
350 config RAM_CODE_SUPPORT
354 If enabled, coreboot discovers RAM configuration (value obtained by
355 reading board straps) and stores it in coreboot table.
357 config BOOTSPLASH_IMAGE
358 bool "Add a bootsplash image"
360 Select this option if you have a bootsplash image that you would
361 like to add to your ROM.
363 This will only add the image to the ROM. To actually run it check
364 options under 'Display' section.
366 config BOOTSPLASH_FILE
367 string "Bootsplash path and filename"
368 depends on BOOTSPLASH_IMAGE
369 default "bootsplash.jpg"
371 The path and filename of the file to use as graphical bootsplash
372 screen. The file format has to be jpg.
376 source "src/acpi/Kconfig"
380 source "src/mainboard/Kconfig"
382 # defaults for CBFS_SIZE are set at the end of the file.
384 hex "Size of CBFS filesystem in ROM"
386 This is the part of the ROM actually managed by CBFS, located at the
387 end of the ROM (passed through cbfstool -o) on x86 and at at the start
388 of the ROM (passed through cbfstool -s) everywhere else. It defaults
389 to span the whole ROM on all but Intel systems that use an Intel Firmware
390 Descriptor. It can be overridden to make coreboot live alongside other
391 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
395 string "fmap description file in fmd format"
396 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
399 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
400 but in some cases more complex setups are required.
401 When an fmd is specified, it overrides the default format.
405 # load site-local kconfig to allow user specific defaults and overrides
406 source "site-local/Kconfig"
408 config SYSTEM_TYPE_LAPTOP
412 config CBFS_AUTOGEN_ATTRIBUTES
416 If this option is selected, every file in cbfs which has a constraint
417 regarding position or alignment will get an additional file attribute
418 which describes this constraint.
423 source "src/soc/*/*/Kconfig"
425 source "src/cpu/Kconfig"
426 comment "Northbridge"
427 source "src/northbridge/*/*/Kconfig"
428 comment "Southbridge"
429 source "src/southbridge/*/*/Kconfig"
431 source "src/superio/*/Kconfig"
432 comment "Embedded Controllers"
433 source "src/ec/acpi/Kconfig"
434 source "src/ec/*/*/Kconfig"
435 # FIXME move to vendorcode
436 source "src/drivers/intel/fsp1_0/Kconfig"
438 source "src/southbridge/intel/common/firmware/Kconfig"
439 source "src/vendorcode/*/Kconfig"
441 source "src/arch/*/Kconfig"
445 source "src/device/Kconfig"
447 menu "Generic Drivers"
448 source "src/drivers/*/Kconfig"
449 source "src/drivers/*/*/Kconfig"
459 select LPC_TPM if ARCH_X86
460 select I2C_TPM if ARCH_ARM
461 select I2C_TPM if ARCH_ARM64
463 Enable this option to enable TPM support in coreboot.
478 default 0x1000 if ARCH_X86
485 config MMCONF_SUPPORT_DEFAULT
489 config MMCONF_SUPPORT
493 config BOOTMODE_STRAPS
497 source "src/console/Kconfig"
499 config HAVE_ACPI_RESUME
503 config RESUME_PATH_SAME_AS_BOOT
505 default y if ARCH_X86
506 depends on HAVE_ACPI_RESUME
508 This option indicates that when a system resumes it takes the
509 same path as a regular boot. e.g. an x86 system runs from the
510 reset vector at 0xfffffff0 on both resume and warm/cold boot.
512 config HAVE_HARD_RESET
516 This variable specifies whether a given board has a hard_reset
517 function, no matter if it's provided by board code or chipset code.
519 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
523 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
527 This should be enabled on certain plaforms, such as the AMD
528 SR565x, that cannot handle concurrent CBFS accesses from
529 multiple APs during early startup.
531 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
535 config HAVE_MONOTONIC_TIMER
538 The board/chipset provides a monotonic timer.
540 config GENERIC_UDELAY
542 depends on HAVE_MONOTONIC_TIMER
544 The board/chipset uses a generic udelay function utilizing the
549 depends on HAVE_MONOTONIC_TIMER
551 Provide a timer queue for performing time-based callbacks.
553 config COOP_MULTITASKING
555 depends on TIMER_QUEUE && ARCH_X86
557 Cooperative multitasking allows callbacks to be multiplexed on the
558 main thread of ramstage. With this enabled it allows for multiple
559 execution paths to take place when they have udelay() calls within
565 depends on COOP_MULTITASKING
567 How many execution threads to cooperatively multitask with.
569 config HAVE_OPTION_TABLE
573 This variable specifies whether a given board has a cmos.layout
574 file containing NVRAM/CMOS bit definitions.
575 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
581 config HAVE_SMI_HANDLER
585 config PCI_IO_CFG_EXT
593 config CACHE_ROM_SIZE_OVERRIDE
597 # TODO: Can probably be removed once all chipsets have kconfig options for it.
602 config USE_WATCHDOG_ON_BOOT
610 Build board-specific VGA code.
616 Enable Unified Memory Architecture for graphics.
618 config HAVE_ACPI_TABLES
621 This variable specifies whether a given board has ACPI table support.
622 It is usually set in mainboard/*/Kconfig.
627 This variable specifies whether a given board has MP table support.
628 It is usually set in mainboard/*/Kconfig.
629 Whether or not the MP table is actually generated by coreboot
630 is configurable by the user via GENERATE_MP_TABLE.
632 config HAVE_PIRQ_TABLE
635 This variable specifies whether a given board has PIRQ table support.
636 It is usually set in mainboard/*/Kconfig.
637 Whether or not the PIRQ table is actually generated by coreboot
638 is configurable by the user via GENERATE_PIRQ_TABLE.
640 config MAX_PIRQ_LINKS
644 This variable specifies the number of PIRQ interrupt links which are
645 routable. On most chipsets, this is 4, INTA through INTD. Some
646 chipsets offer more than four links, commonly up to INTH. They may
647 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
648 table specifies links greater than 4, pirq_route_irqs will not
649 function properly, unless this variable is correctly set.
659 Build support for NHLT (non HD Audio) ACPI table generation.
662 config COREBOOT_TABLE_SIZE
664 default 0x8000 if ARCH_X86
665 default 0x2000 if !ARCH_X86
667 The amount of memory to reserve for the coreboot tables in
670 #These Options are here to avoid "undefined" warnings.
671 #The actual selection and help texts are in the following menu.
675 config GENERATE_MP_TABLE
676 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
678 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
680 Generate an MP table (conforming to the Intel MultiProcessor
681 specification 1.4) for this board.
685 config GENERATE_PIRQ_TABLE
686 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
688 default HAVE_PIRQ_TABLE
690 Generate a PIRQ table for this board.
694 config GENERATE_SMBIOS_TABLES
696 bool "Generate SMBIOS tables"
699 Generate SMBIOS tables for this board.
703 config SMBIOS_PROVIDED_BY_MOBO
707 config MAINBOARD_SERIAL_NUMBER
708 string "SMBIOS Serial Number"
709 depends on GENERATE_SMBIOS_TABLES
710 depends on !SMBIOS_PROVIDED_BY_MOBO
713 The Serial Number to store in SMBIOS structures.
715 config MAINBOARD_VERSION
716 string "SMBIOS Version Number"
717 depends on GENERATE_SMBIOS_TABLES
718 depends on !SMBIOS_PROVIDED_BY_MOBO
721 The Version Number to store in SMBIOS structures.
723 config MAINBOARD_SMBIOS_MANUFACTURER
724 string "SMBIOS Manufacturer"
725 depends on GENERATE_SMBIOS_TABLES
726 depends on !SMBIOS_PROVIDED_BY_MOBO
727 default MAINBOARD_VENDOR
729 Override the default Manufacturer stored in SMBIOS structures.
731 config MAINBOARD_SMBIOS_PRODUCT_NAME
732 string "SMBIOS Product name"
733 depends on GENERATE_SMBIOS_TABLES
734 depends on !SMBIOS_PROVIDED_BY_MOBO
735 default MAINBOARD_PART_NUMBER
737 Override the default Product name stored in SMBIOS structures.
741 source "payloads/Kconfig"
745 # TODO: Better help text and detailed instructions.
747 bool "GDB debugging support"
749 depends on CONSOLE_SERIAL
751 If enabled, you will be able to set breakpoints for gdb debugging.
752 See src/arch/x86/lib/c_start.S for details.
755 bool "Wait for a GDB connection"
759 If enabled, coreboot will wait for a GDB connection.
762 bool "Halt when hitting a BUG() or assertion error"
765 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
768 bool "Output verbose CBFS debug messages"
771 This option enables additional CBFS related debug messages.
773 config HAVE_DEBUG_RAM_SETUP
776 config DEBUG_RAM_SETUP
777 bool "Output verbose RAM init debug messages"
779 depends on HAVE_DEBUG_RAM_SETUP
781 This option enables additional RAM init related debug messages.
782 It is recommended to enable this when debugging issues on your
783 board which might be RAM init related.
785 Note: This option will increase the size of the coreboot image.
789 config HAVE_DEBUG_CAR
794 depends on HAVE_DEBUG_CAR
796 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
797 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
798 # printk(BIOS_DEBUG, ...) calls.
800 bool "Output verbose Cache-as-RAM debug messages"
802 depends on HAVE_DEBUG_CAR
804 This option enables additional CAR related debug messages.
808 bool "Check PIRQ table consistency"
810 depends on GENERATE_PIRQ_TABLE
814 config HAVE_DEBUG_SMBUS
818 bool "Output verbose SMBus debug messages"
820 depends on HAVE_DEBUG_SMBUS
822 This option enables additional SMBus (and SPD) debug messages.
824 Note: This option will increase the size of the coreboot image.
829 bool "Output verbose SMI debug messages"
831 depends on HAVE_SMI_HANDLER
832 select SPI_FLASH_SMM if SPI_CONSOLE
834 This option enables additional SMI related debug messages.
836 Note: This option will increase the size of the coreboot image.
840 config DEBUG_SMM_RELOCATION
841 bool "Debug SMM relocation code"
843 depends on HAVE_SMI_HANDLER
845 This option enables additional SMM handler relocation related
848 Note: This option will increase the size of the coreboot image.
852 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
853 # printk(BIOS_DEBUG, ...) calls.
855 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
859 This option enables additional malloc related debug messages.
861 Note: This option will increase the size of the coreboot image.
865 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
866 # printk(BIOS_DEBUG, ...) calls.
868 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
872 This option enables additional ACPI related debug messages.
874 Note: This option will slightly increase the size of the coreboot image.
878 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
879 # printk(BIOS_DEBUG, ...) calls.
880 config REALMODE_DEBUG
881 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
884 depends on PCI_OPTION_ROM_RUN_REALMODE
886 This option enables additional x86emu related debug messages.
888 Note: This option will increase the time to emulate a ROM.
893 bool "Output verbose x86emu debug messages"
895 depends on PCI_OPTION_ROM_RUN_YABEL
897 This option enables additional x86emu related debug messages.
899 Note: This option will increase the size of the coreboot image.
903 config X86EMU_DEBUG_JMP
904 bool "Trace JMP/RETF"
906 depends on X86EMU_DEBUG
908 Print information about JMP and RETF opcodes from x86emu.
910 Note: This option will increase the size of the coreboot image.
914 config X86EMU_DEBUG_TRACE
915 bool "Trace all opcodes"
917 depends on X86EMU_DEBUG
919 Print _all_ opcodes that are executed by x86emu.
921 WARNING: This will produce a LOT of output and take a long time.
923 Note: This option will increase the size of the coreboot image.
927 config X86EMU_DEBUG_PNP
928 bool "Log Plug&Play accesses"
930 depends on X86EMU_DEBUG
932 Print Plug And Play accesses made by option ROMs.
934 Note: This option will increase the size of the coreboot image.
938 config X86EMU_DEBUG_DISK
941 depends on X86EMU_DEBUG
943 Print Disk I/O related messages.
945 Note: This option will increase the size of the coreboot image.
949 config X86EMU_DEBUG_PMM
952 depends on X86EMU_DEBUG
954 Print messages related to POST Memory Manager (PMM).
956 Note: This option will increase the size of the coreboot image.
961 config X86EMU_DEBUG_VBE
962 bool "Debug VESA BIOS Extensions"
964 depends on X86EMU_DEBUG
966 Print messages related to VESA BIOS Extension (VBE) functions.
968 Note: This option will increase the size of the coreboot image.
972 config X86EMU_DEBUG_INT10
973 bool "Redirect INT10 output to console"
975 depends on X86EMU_DEBUG
977 Let INT10 (i.e. character output) calls print messages to debug output.
979 Note: This option will increase the size of the coreboot image.
983 config X86EMU_DEBUG_INTERRUPTS
984 bool "Log intXX calls"
986 depends on X86EMU_DEBUG
988 Print messages related to interrupt handling.
990 Note: This option will increase the size of the coreboot image.
994 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
995 bool "Log special memory accesses"
997 depends on X86EMU_DEBUG
999 Print messages related to accesses to certain areas of the virtual
1000 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1002 Note: This option will increase the size of the coreboot image.
1006 config X86EMU_DEBUG_MEM
1007 bool "Log all memory accesses"
1009 depends on X86EMU_DEBUG
1011 Print memory accesses made by option ROM.
1012 Note: This also includes accesses to fetch instructions.
1014 Note: This option will increase the size of the coreboot image.
1018 config X86EMU_DEBUG_IO
1019 bool "Log IO accesses"
1021 depends on X86EMU_DEBUG
1023 Print I/O accesses made by option ROM.
1025 Note: This option will increase the size of the coreboot image.
1029 config X86EMU_DEBUG_TIMINGS
1030 bool "Output timing information"
1032 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1034 Print timing information needed by i915tool.
1039 bool "Output verbose TPM debug messages"
1043 This option enables additional TPM related debug messages.
1045 config DEBUG_SPI_FLASH
1046 bool "Output verbose SPI flash debug messages"
1048 depends on SPI_FLASH
1050 This option enables additional SPI flash related debug messages.
1052 config DEBUG_USBDEBUG
1053 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1057 This option enables additional USB 2.0 debug dongle related messages.
1059 Select this to debug the connection of usbdebug dongle. Note that
1060 you need some other working console to receive the messages.
1062 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1063 # Only visible with the right southbridge and loglevel.
1064 config DEBUG_INTEL_ME
1065 bool "Verbose logging for Intel Management Engine"
1068 Enable verbose logging for Intel Management Engine driver that
1069 is present on Intel 6-series chipsets.
1073 bool "Trace function calls"
1076 If enabled, every function will print information to console once
1077 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1078 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1079 of calling function. Please note some printk related functions
1080 are omitted from trace to have good looking console dumps.
1082 config DEBUG_COVERAGE
1083 bool "Debug code coverage"
1087 If enabled, the code coverage hooks in coreboot will output some
1088 information about the coverage data that is dumped.
1092 # These probably belong somewhere else, but they are needed somewhere.
1093 config ENABLE_APIC_EXT_ID
1097 config WARNINGS_ARE_ERRORS
1101 # TODO: Remove this when all platforms are fixed.
1102 config IASL_WARNINGS_ARE_ERRORS
1105 Select to Fail the build if a IASL generates a warning.
1106 This will be defaulted to disabled for the platforms that
1107 currently fail. This allows the REST of the platforms to
1108 have this check enabled while we're working to get those
1111 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1114 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1115 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1116 # mutually exclusive. One of these options must be selected in the
1117 # mainboard Kconfig if the chipset supports enabling and disabling of
1118 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1119 # in mainboard/Kconfig to know if the button should be enabled or not.
1121 config POWER_BUTTON_DEFAULT_ENABLE
1124 Select when the board has a power button which can optionally be
1125 disabled by the user.
1127 config POWER_BUTTON_DEFAULT_DISABLE
1130 Select when the board has a power button which can optionally be
1131 enabled by the user, e.g. when the board ships with a jumper over
1132 the power switch contacts.
1134 config POWER_BUTTON_FORCE_ENABLE
1137 Select when the board requires that the power button is always
1140 config POWER_BUTTON_FORCE_DISABLE
1143 Select when the board requires that the power button is always
1144 disabled, e.g. when it has been hardwired to ground.
1146 config POWER_BUTTON_IS_OPTIONAL
1148 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1149 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1151 Internal option that controls ENABLE_POWER_BUTTON visibility.
1157 Internal option that controls whether we compile in register scripts.
1159 config MAX_REBOOT_CNT
1163 Internal option that sets the maximum number of bootblock executions allowed
1164 with the normal image enabled before assuming the normal image is defective
1165 and switching to the fallback image.
1171 This is the part of the ROM actually managed by CBFS. Set it to be
1172 equal to the full rom size if that hasn't been overridden by the
1173 chipset or mainboard.
1175 config DEBUG_BOOT_STATE
1179 Control debugging of the boot state machine. When selected displays
1180 the state boundaries in ramstage.