1 ## SPDX-License-Identifier: GPL-2.0-only
3 mainmenu "coreboot configuration"
12 string "Local version string"
14 Append an extra string to the end of the coreboot version.
16 This can be useful if, for instance, you want to append the
17 respective board's hostname or some other identifying string to
18 the coreboot version number, so that you can easily distinguish
19 boot logs of different boards from each other.
21 config CONFIGURABLE_CBFS_PREFIX
24 Select this to prompt to use to configure the prefix for cbfs files.
27 prompt "CBFS prefix to use"
28 depends on CONFIGURABLE_CBFS_PREFIX
29 default CBFS_PREFIX_FALLBACK
31 config CBFS_PREFIX_FALLBACK
34 config CBFS_PREFIX_NORMAL
37 config CBFS_PREFIX_DIY
38 bool "Define your own cbfs prefix"
43 string "CBFS prefix to use" if CBFS_PREFIX_DIY
44 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
45 default "normal" if CBFS_PREFIX_NORMAL
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
51 prompt "Compiler to use"
54 This option allows you to select the compiler used for building
56 You must build the coreboot crosscompiler for the board that you
59 To build all the GCC crosscompilers (takes a LONG time), run:
62 For help on individual architectures, run the command:
68 Use the GNU Compiler Collection (GCC) to build coreboot.
70 For details see http://gcc.gnu.org.
72 config COMPILER_LLVM_CLANG
73 bool "LLVM/clang (TESTING ONLY - Not currently working)"
75 Use LLVM/clang to build coreboot. To use this, you must build the
76 coreboot version of the clang compiler. Run the command
78 Note that this option is not currently working correctly and should
79 really only be selected if you're trying to work on getting clang
82 For details see http://clang.llvm.org.
87 bool "Allow building with any toolchain"
90 Many toolchains break when building coreboot since it uses quite
91 unusual linker features. Unless developers explicitely request it,
92 we'll have to assume that they use their distro compiler by mistake.
93 Make sure that using patched compilers is a conscious decision.
96 bool "Use ccache to speed up (re)compilation"
99 Enables the use of ccache for faster builds.
101 Requires the ccache utility in your system $PATH.
103 For details see https://ccache.samba.org.
106 bool "Generate flashmap descriptor parser using flex and bison"
109 Enable this option if you are working on the flashmap descriptor
110 parser and made changes to fmd_scanner.l or fmd_parser.y.
112 Otherwise, say N to use the provided pregenerated scanner/parser.
114 config UTIL_GENPARSER
115 bool "Generate SCONFIG & BINCFG parser using flex and bison"
118 Enable this option if you are working on the sconfig device tree
119 parser or bincfg and made changes to the .l or .y files.
121 Otherwise, say N to use the provided pregenerated scanner/parser.
123 config USE_OPTION_TABLE
124 bool "Use CMOS for configuration values"
125 depends on HAVE_OPTION_TABLE
127 Enable this option if coreboot shall read options from the "CMOS"
128 NVRAM instead of using hard-coded values.
130 config STATIC_OPTION_TABLE
131 bool "Load default configuration values into CMOS on each boot"
132 depends on USE_OPTION_TABLE
134 Enable this option to reset "CMOS" NVRAM values to default on
135 every boot. Use this if you want the NVRAM configuration to
136 never be modified from its default values.
138 config COMPRESS_RAMSTAGE
139 bool "Compress ramstage with LZMA"
140 depends on HAVE_RAMSTAGE
141 # Default value set at the end of the file
143 Compress ramstage to save memory in the flash image.
145 config COMPRESS_PRERAM_STAGES
146 bool "Compress romstage and verstage with LZ4"
147 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
148 # Default value set at the end of the file
150 Compress romstage and (if it exists) verstage with LZ4 to save flash
151 space and speed up boot, since the time for reading the image from SPI
152 (and in the vboot case verifying it) is usually much greater than the
153 time spent decompressing. Doesn't work for XIP stages (assume all
154 ARCH_X86 for now) for obvious reasons.
156 config COMPRESS_BOOTBLOCK
158 depends on HAVE_BOOTBLOCK
160 This option can be used to compress the bootblock with LZ4 and attach
161 a small self-decompression stub to its front. This can drastically
162 reduce boot time on platforms where the bootblock is loaded over a
163 very slow connection and bootblock size trumps all other factors for
164 speed. Since using this option usually requires changes to the
165 SoC memlayout and possibly extra support code, it should not be
166 user-selectable. (There's no real point in offering this to the user
167 anyway... if it works and saves boot time, you would always want it.)
169 config INCLUDE_CONFIG_FILE
170 bool "Include the coreboot .config file into the ROM image"
171 # Default value set at the end of the file
173 Include the .config file that was used to compile coreboot
174 in the (CBFS) ROM image. This is useful if you want to know which
175 options were used to build a specific coreboot.rom image.
177 Saying Y here will increase the image size by 2-3KB.
179 You can use the following command to easily list the options:
181 grep -a CONFIG_ coreboot.rom
183 Alternatively, you can also use cbfstool to print the image
184 contents (including the raw 'config' item we're looking for).
188 $ cbfstool coreboot.rom print
189 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
193 Name Offset Type Size
194 cmos_layout.bin 0x0 CMOS layout 1159
195 fallback/romstage 0x4c0 stage 339756
196 fallback/ramstage 0x53440 stage 186664
197 fallback/payload 0x80dc0 payload 51526
198 config 0x8d740 raw 3324
199 (empty) 0x8e480 null 3610440
201 config COLLECT_TIMESTAMPS
202 bool "Create a table of timestamps collected during boot"
203 default y if ARCH_X86
205 Make coreboot create a table of timer-ID/timer-value pairs to
206 allow measuring time spent at different phases of the boot process.
208 config TIMESTAMPS_ON_CONSOLE
209 bool "Print the timestamp values on the console"
211 depends on COLLECT_TIMESTAMPS
213 Print the timestamps to the debug console if enabled at level info.
216 bool "Allow use of binary-only repository"
219 This draws in the blobs repository, which contains binary files that
220 might be required for some chipsets or boards.
221 This flag ensures that a "Free" option remains available for users.
224 bool "Allow AMD blobs repository (with license agreement)"
227 This draws in the amd_blobs repository, which contains binary files
228 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
229 etc. Selecting this item to download or clone the repo implies your
230 agreement to the AMD license agreement. A copy of the license text
231 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
232 and your copy of the license is present in the repo once downloaded.
234 Note that for some products, omitting PSP, SMU images, or other items
235 may result in a nonbooting coreboot.rom.
238 bool "Allow QC blobs repository (selecting this agrees to the license!)"
241 This draws in the qc_blobs repository, which contains binary files
242 distributed by Qualcomm that are required to build firmware for
243 certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP
244 firmware). If you say Y here you are implicitly agreeing to the
245 Qualcomm license agreement which can be found at:
246 https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE
248 *****************************************************
249 PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN
250 ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION!
251 *****************************************************
253 Not selecting this option means certain Qualcomm SoCs and related
254 mainboards cannot be built and will be hidden from the "Mainboards"
258 bool "Code coverage support"
259 depends on COMPILER_GCC
261 Add code coverage support for coreboot. This will store code
262 coverage information in CBMEM for extraction from user space.
266 bool "Undefined behavior sanitizer support"
269 Instrument the code with checks for undefined behavior. If unsure,
270 say N because it adds a small performance penalty and may abort
271 on code that happens to work in spite of the UB.
274 prompt "Stage Cache for ACPI S3 resume"
275 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
276 default TSEG_STAGE_CACHE if SMM_TSEG
278 config NO_STAGE_CACHE
281 Do not save any component in stage cache for resume path. On resume,
282 all components would be read back from CBFS again.
284 config TSEG_STAGE_CACHE
288 The option enables stage cache support for platform. Platform
289 can stash copies of postcar, ramstage and raw runtime data
290 inside SMM TSEG, to be restored on S3 resume path.
292 config CBMEM_STAGE_CACHE
296 The option enables stage cache support for platform. Platform
297 can stash copies of postcar, ramstage and raw runtime data
300 While the approach is faster than reloading stages from boot media
301 it is also a possible attack scenario via which OS can possibly
302 circumvent SMM locks and SPI write protections.
304 If unsure, select 'N'
309 bool "Update existing coreboot.rom image"
311 If this option is enabled, no new coreboot.rom file
312 is created. Instead it is expected that there already
313 is a suitable file for further processing.
314 The bootblock will not be modified.
316 If unsure, select 'N'
318 config BOOTSPLASH_IMAGE
319 bool "Add a bootsplash image"
321 Select this option if you have a bootsplash image that you would
322 like to add to your ROM.
324 This will only add the image to the ROM. To actually run it check
325 options under 'Display' section.
327 config BOOTSPLASH_FILE
328 string "Bootsplash path and filename"
329 depends on BOOTSPLASH_IMAGE
330 # Default value set at the end of the file
332 The path and filename of the file to use as graphical bootsplash
333 screen. The file format has to be jpg.
336 bool "Firmware Configuration Probing"
339 Enable support for probing devices with fw_config. This is a simple
340 bitmask broken into fields and options for probing.
342 config FW_CONFIG_SOURCE_CBFS
343 bool "Obtain Firmware Configuration value from CBFS"
347 With this option enabled coreboot will look for the 32bit firmware
348 configuration value in CBFS at the selected prefix with the file name
349 "fw_config". This option will override other sources and allow the
350 local image to preempt the mainboard selected source.
352 config FW_CONFIG_SOURCE_CHROMEEC_CBI
353 bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
354 depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
357 This option tells coreboot to read the firmware configuration value
358 from the Google Chrome Embedded Controller CBI interface. This source
359 is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
362 config HAVE_RAMPAYLOAD
366 bool "Enable coreboot flow without executing ramstage"
367 default y if ARCH_X86
368 depends on HAVE_RAMPAYLOAD
370 If this option is enabled, coreboot flow will skip ramstage
371 loading and execution of ramstage to load payload.
373 Instead it is expected to load payload from postcar stage itself.
375 In this flow coreboot will perform basic x86 initialization
376 (DRAM resource allocation), MTRR programming,
377 Skip PCI enumeration logic and only allocate BAR for fixed devices
378 (bootable devices, TPM over GSPI).
380 config HAVE_CONFIGURABLE_RAMSTAGE
383 config CONFIGURABLE_RAMSTAGE
384 bool "Enable a configurable ramstage."
385 default y if ARCH_X86
386 depends on HAVE_CONFIGURABLE_RAMSTAGE
388 A configurable ramstage allows you to select which parts of the ramstage
389 to run. Currently, we can only select a minimal PCI scanning step.
390 The minimal PCI scanning will only check those parts that are enabled
391 in the devicetree.cb. By convention none of those devices should be bridges.
393 config MINIMAL_PCI_SCANNING
394 bool "Enable minimal PCI scanning"
395 depends on CONFIGURABLE_RAMSTAGE && PCI
397 If this option is enabled, coreboot will scan only PCI devices
398 marked as mandatory in devicetree.cb
403 source "src/mainboard/Kconfig"
407 default "devicetree.cb"
409 This symbol allows mainboards to select a different file under their
410 mainboard directory for the devicetree.cb file. This allows the board
411 variants that need different devicetrees to be in the same directory.
413 Examples: "devicetree.variant.cb"
414 "variant/devicetree.cb"
416 config OVERRIDE_DEVICETREE
420 This symbol allows variants to provide an override devicetree file to
421 override the registers and/or add new devices on top of the ones
422 provided by baseboard devicetree using CONFIG_DEVICETREE.
424 Examples: "devicetree.variant-override.cb"
425 "variant/devicetree-override.cb"
428 string "fmap description file in fmd format"
429 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
432 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
433 but in some cases more complex setups are required.
434 When an fmd is specified, it overrides the default format.
437 hex "Size of CBFS filesystem in ROM"
438 depends on FMDFILE = ""
439 # Default value set at the end of the file
441 This is the part of the ROM actually managed by CBFS, located at the
442 end of the ROM (passed through cbfstool -o) on x86 and at at the start
443 of the ROM (passed through cbfstool -s) everywhere else. It defaults
444 to span the whole ROM on all but Intel systems that use an Intel Firmware
445 Descriptor. It can be overridden to make coreboot live alongside other
446 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
447 binaries. This symbol should only be used to generate a default FMAP and
448 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
452 # load site-local kconfig to allow user specific defaults and overrides
453 source "site-local/Kconfig"
455 config SYSTEM_TYPE_LAPTOP
459 config SYSTEM_TYPE_TABLET
463 config SYSTEM_TYPE_DETACHABLE
467 config SYSTEM_TYPE_CONVERTIBLE
471 config CBFS_AUTOGEN_ATTRIBUTES
475 If this option is selected, every file in cbfs which has a constraint
476 regarding position or alignment will get an additional file attribute
477 which describes this constraint.
482 source "src/soc/*/Kconfig"
484 source "src/cpu/Kconfig"
485 comment "Northbridge"
486 source "src/northbridge/*/*/Kconfig"
487 comment "Southbridge"
488 source "src/southbridge/*/*/Kconfig"
490 source "src/superio/*/*/Kconfig"
491 comment "Embedded Controllers"
492 source "src/ec/acpi/Kconfig"
493 source "src/ec/*/*/Kconfig"
495 source "src/southbridge/intel/common/firmware/Kconfig"
496 source "src/vendorcode/*/Kconfig"
498 source "src/arch/*/Kconfig"
502 source "src/device/Kconfig"
504 menu "Generic Drivers"
505 source "src/drivers/*/Kconfig"
506 source "src/drivers/*/*/Kconfig"
507 source "src/commonlib/storage/Kconfig"
512 source "src/security/Kconfig"
513 source "src/vendorcode/eltan/security/Kconfig"
517 source "src/acpi/Kconfig"
519 # This option is for the current boards/chipsets where SPI flash
520 # is not the boot device. Currently nearly all boards/chipsets assume
521 # SPI flash is the boot device.
522 config BOOT_DEVICE_NOT_SPI_FLASH
526 config BOOT_DEVICE_SPI_FLASH
528 default y if !BOOT_DEVICE_NOT_SPI_FLASH
531 config BOOT_DEVICE_MEMORY_MAPPED
533 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
536 Inform system if SPI is memory-mapped or not.
538 config BOOT_DEVICE_SUPPORTS_WRITES
542 Indicate that the platform has writable boot device
551 default 0x100000 if FLATTENED_DEVICE_TREE
556 default 0x1000 if ARCH_X86
563 source "src/console/Kconfig"
565 config HAVE_ACPI_RESUME
569 config DISABLE_ACPI_HIBERNATE
573 Removes S4 from the available sleepstates
575 config RESUME_PATH_SAME_AS_BOOT
577 default y if ARCH_X86
578 depends on HAVE_ACPI_RESUME
580 This option indicates that when a system resumes it takes the
581 same path as a regular boot. e.g. an x86 system runs from the
582 reset vector at 0xfffffff0 on both resume and warm/cold boot.
584 config NO_MONOTONIC_TIMER
587 config HAVE_MONOTONIC_TIMER
589 depends on !NO_MONOTONIC_TIMER
592 The board/chipset provides a monotonic timer.
594 config GENERIC_UDELAY
596 depends on HAVE_MONOTONIC_TIMER
597 default y if !ARCH_X86
599 The board/chipset uses a generic udelay function utilizing the
604 depends on HAVE_MONOTONIC_TIMER
606 Provide a timer queue for performing time-based callbacks.
608 config COOP_MULTITASKING
610 depends on TIMER_QUEUE && ARCH_X86
612 Cooperative multitasking allows callbacks to be multiplexed on the
613 main thread of ramstage. With this enabled it allows for multiple
614 execution paths to take place when they have udelay() calls within
620 depends on COOP_MULTITASKING
622 How many execution threads to cooperatively multitask with.
624 config HAVE_OPTION_TABLE
628 This variable specifies whether a given board has a cmos.layout
629 file containing NVRAM/CMOS bit definitions.
630 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
632 config PCI_IO_CFG_EXT
640 config USE_WATCHDOG_ON_BOOT
648 Enable Unified Memory Architecture for graphics.
653 This variable specifies whether a given board has MP table support.
654 It is usually set in mainboard/*/Kconfig.
655 Whether or not the MP table is actually generated by coreboot
656 is configurable by the user via GENERATE_MP_TABLE.
658 config HAVE_PIRQ_TABLE
661 This variable specifies whether a given board has PIRQ table support.
662 It is usually set in mainboard/*/Kconfig.
663 Whether or not the PIRQ table is actually generated by coreboot
664 is configurable by the user via GENERATE_PIRQ_TABLE.
670 Build support for NHLT (non HD Audio) ACPI table generation.
672 #These Options are here to avoid "undefined" warnings.
673 #The actual selection and help texts are in the following menu.
677 config GENERATE_MP_TABLE
678 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
680 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
682 Generate an MP table (conforming to the Intel MultiProcessor
683 specification 1.4) for this board.
687 config GENERATE_PIRQ_TABLE
688 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
690 default HAVE_PIRQ_TABLE
692 Generate a PIRQ table for this board.
696 config GENERATE_SMBIOS_TABLES
698 bool "Generate SMBIOS tables"
701 Generate SMBIOS tables for this board.
705 config SMBIOS_PROVIDED_BY_MOBO
709 config MAINBOARD_SERIAL_NUMBER
710 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
712 depends on GENERATE_SMBIOS_TABLES
715 The Serial Number to store in SMBIOS structures.
717 config MAINBOARD_VERSION
718 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
720 depends on GENERATE_SMBIOS_TABLES
723 The Version Number to store in SMBIOS structures.
725 config MAINBOARD_SMBIOS_MANUFACTURER
726 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
728 depends on GENERATE_SMBIOS_TABLES
729 default MAINBOARD_VENDOR
731 Override the default Manufacturer stored in SMBIOS structures.
733 config MAINBOARD_SMBIOS_PRODUCT_NAME
734 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
736 depends on GENERATE_SMBIOS_TABLES
737 default MAINBOARD_PART_NUMBER
739 Override the default Product name stored in SMBIOS structures.
741 config VPD_SMBIOS_VERSION
742 bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'"
744 depends on VPD && GENERATE_SMBIOS_TABLES
746 Selecting this option will read firmware_version from
747 VPD_RO and override SMBIOS type 0 version. One special
748 scenario of using this feature is to assign a BIOS version
749 to a coreboot image without the need to rebuild from source.
753 source "payloads/Kconfig"
757 comment "CPU Debug Settings"
758 source "src/cpu/*/Kconfig.debug_cpu"
760 comment "BLOB Debug Settings"
761 source "src/drivers/intel/fsp*/Kconfig.debug_blob"
763 comment "General Debug Settings"
765 # TODO: Better help text and detailed instructions.
767 bool "GDB debugging support"
769 depends on DRIVERS_UART
771 If enabled, you will be able to set breakpoints for gdb debugging.
772 See src/arch/x86/lib/c_start.S for details.
775 bool "Wait for a GDB connection in the ramstage"
779 If enabled, coreboot will wait for a GDB connection in the ramstage.
783 bool "Halt when hitting a BUG() or assertion error"
786 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
788 config HAVE_DEBUG_GPIO
792 bool "Output verbose GPIO debug messages"
793 depends on HAVE_DEBUG_GPIO
796 bool "Output verbose CBFS debug messages"
799 This option enables additional CBFS related debug messages.
801 config HAVE_DEBUG_RAM_SETUP
804 config DEBUG_RAM_SETUP
805 bool "Output verbose RAM init debug messages"
807 depends on HAVE_DEBUG_RAM_SETUP
809 This option enables additional RAM init related debug messages.
810 It is recommended to enable this when debugging issues on your
811 board which might be RAM init related.
813 Note: This option will increase the size of the coreboot image.
818 bool "Check PIRQ table consistency"
820 depends on GENERATE_PIRQ_TABLE
824 config HAVE_DEBUG_SMBUS
828 bool "Output verbose SMBus debug messages"
830 depends on HAVE_DEBUG_SMBUS
832 This option enables additional SMBus (and SPD) debug messages.
834 Note: This option will increase the size of the coreboot image.
839 bool "Output verbose SMI debug messages"
841 depends on HAVE_SMI_HANDLER
842 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
844 This option enables additional SMI related debug messages.
846 Note: This option will increase the size of the coreboot image.
850 config DEBUG_PERIODIC_SMI
851 bool "Trigger SMI periodically"
854 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
855 # printk(BIOS_DEBUG, ...) calls.
857 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
861 This option enables additional malloc related debug messages.
863 Note: This option will increase the size of the coreboot image.
867 config DEBUG_CONSOLE_INIT
868 bool "Debug console initialisation code"
871 With this option printk()'s are attempted before console hardware
872 initialisation has been completed. Your mileage may vary.
874 Typically you will need to modify source in console_hw_init() such
875 that a working console appears before the one you want to debug.
879 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
880 # printk(BIOS_DEBUG, ...) calls.
881 config REALMODE_DEBUG
882 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
885 depends on PCI_OPTION_ROM_RUN_REALMODE
887 This option enables additional x86emu related debug messages.
889 Note: This option will increase the time to emulate a ROM.
894 bool "Output verbose x86emu debug messages"
896 depends on PCI_OPTION_ROM_RUN_YABEL
898 This option enables additional x86emu related debug messages.
900 Note: This option will increase the size of the coreboot image.
904 config X86EMU_DEBUG_JMP
905 bool "Trace JMP/RETF"
907 depends on X86EMU_DEBUG
909 Print information about JMP and RETF opcodes from x86emu.
911 Note: This option will increase the size of the coreboot image.
915 config X86EMU_DEBUG_TRACE
916 bool "Trace all opcodes"
918 depends on X86EMU_DEBUG
920 Print _all_ opcodes that are executed by x86emu.
922 WARNING: This will produce a LOT of output and take a long time.
924 Note: This option will increase the size of the coreboot image.
928 config X86EMU_DEBUG_PNP
929 bool "Log Plug&Play accesses"
931 depends on X86EMU_DEBUG
933 Print Plug And Play accesses made by option ROMs.
935 Note: This option will increase the size of the coreboot image.
939 config X86EMU_DEBUG_DISK
942 depends on X86EMU_DEBUG
944 Print Disk I/O related messages.
946 Note: This option will increase the size of the coreboot image.
950 config X86EMU_DEBUG_PMM
953 depends on X86EMU_DEBUG
955 Print messages related to POST Memory Manager (PMM).
957 Note: This option will increase the size of the coreboot image.
962 config X86EMU_DEBUG_VBE
963 bool "Debug VESA BIOS Extensions"
965 depends on X86EMU_DEBUG
967 Print messages related to VESA BIOS Extension (VBE) functions.
969 Note: This option will increase the size of the coreboot image.
973 config X86EMU_DEBUG_INT10
974 bool "Redirect INT10 output to console"
976 depends on X86EMU_DEBUG
978 Let INT10 (i.e. character output) calls print messages to debug output.
980 Note: This option will increase the size of the coreboot image.
984 config X86EMU_DEBUG_INTERRUPTS
985 bool "Log intXX calls"
987 depends on X86EMU_DEBUG
989 Print messages related to interrupt handling.
991 Note: This option will increase the size of the coreboot image.
995 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
996 bool "Log special memory accesses"
998 depends on X86EMU_DEBUG
1000 Print messages related to accesses to certain areas of the virtual
1001 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1003 Note: This option will increase the size of the coreboot image.
1007 config X86EMU_DEBUG_MEM
1008 bool "Log all memory accesses"
1010 depends on X86EMU_DEBUG
1012 Print memory accesses made by option ROM.
1013 Note: This also includes accesses to fetch instructions.
1015 Note: This option will increase the size of the coreboot image.
1019 config X86EMU_DEBUG_IO
1020 bool "Log IO accesses"
1022 depends on X86EMU_DEBUG
1024 Print I/O accesses made by option ROM.
1026 Note: This option will increase the size of the coreboot image.
1030 config X86EMU_DEBUG_TIMINGS
1031 bool "Output timing information"
1033 depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
1035 Print timing information needed by i915tool.
1039 config DEBUG_SPI_FLASH
1040 bool "Output verbose SPI flash debug messages"
1042 depends on SPI_FLASH
1044 This option enables additional SPI flash related debug messages.
1046 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1047 # Only visible with the right southbridge and loglevel.
1048 config DEBUG_INTEL_ME
1049 bool "Verbose logging for Intel Management Engine"
1052 Enable verbose logging for Intel Management Engine driver that
1053 is present on Intel 6-series chipsets.
1057 bool "Trace function calls"
1060 If enabled, every function will print information to console once
1061 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1062 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1063 of calling function. Please note some printk related functions
1064 are omitted from trace to have good looking console dumps.
1066 config DEBUG_COVERAGE
1067 bool "Debug code coverage"
1071 If enabled, the code coverage hooks in coreboot will output some
1072 information about the coverage data that is dumped.
1074 config DEBUG_BOOT_STATE
1075 bool "Debug boot state machine"
1078 Control debugging of the boot state machine. When selected displays
1079 the state boundaries in ramstage.
1081 config DEBUG_ADA_CODE
1082 bool "Compile debug code in Ada sources"
1085 Add the compiler switch `-gnata` to compile code guarded by
1088 config HAVE_EM100_SUPPORT
1089 bool "Platform can support the Dediprog EM100 SPI emulator"
1091 This is enabled by platforms which can support using the EM100.
1094 bool "Configure image for EM100 usage"
1095 depends on HAVE_EM100_SUPPORT
1097 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1098 over USB. However it only supports a maximum SPI clock of 20MHz and
1099 single data output. Enable this option to use a 20MHz SPI clock and
1100 disable "Dual Output Fast Read" Support.
1102 On AMD platforms this changes the SPI speed at run-time if the
1103 mainboard code supports this. On supported Intel platforms this works
1104 by changing the settings in the descriptor.bin file.
1109 ###############################################################################
1110 # Set variables with no prompt - these can be set anywhere, and putting at
1111 # the end of this file gives the most flexibility.
1113 source "src/lib/Kconfig"
1115 config WARNINGS_ARE_ERRORS
1119 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1120 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1121 # mutually exclusive. One of these options must be selected in the
1122 # mainboard Kconfig if the chipset supports enabling and disabling of
1123 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1124 # in mainboard/Kconfig to know if the button should be enabled or not.
1126 config POWER_BUTTON_DEFAULT_ENABLE
1129 Select when the board has a power button which can optionally be
1130 disabled by the user.
1132 config POWER_BUTTON_DEFAULT_DISABLE
1135 Select when the board has a power button which can optionally be
1136 enabled by the user, e.g. when the board ships with a jumper over
1137 the power switch contacts.
1139 config POWER_BUTTON_FORCE_ENABLE
1142 Select when the board requires that the power button is always
1145 config POWER_BUTTON_FORCE_DISABLE
1148 Select when the board requires that the power button is always
1149 disabled, e.g. when it has been hardwired to ground.
1151 config POWER_BUTTON_IS_OPTIONAL
1153 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1154 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1156 Internal option that controls ENABLE_POWER_BUTTON visibility.
1162 Internal option that controls whether we compile in register scripts.
1164 config MAX_REBOOT_CNT
1168 Internal option that sets the maximum number of bootblock executions allowed
1169 with the normal image enabled before assuming the normal image is defective
1170 and switching to the fallback image.
1172 config UNCOMPRESSED_RAMSTAGE
1175 config NO_XIP_EARLY_STAGES
1177 default n if ARCH_X86
1180 Identify if early stages are eXecute-In-Place(XIP).
1182 config EARLY_CBMEM_LIST
1186 Enable display of CBMEM during romstage and postcar.
1188 config RELOCATABLE_MODULES
1191 If RELOCATABLE_MODULES is selected then support is enabled for
1192 building relocatable modules in the RAM stage. Those modules can be
1193 loaded anywhere and all the relocations are handled automatically.
1195 config GENERIC_GPIO_LIB
1198 If enabled, compile the generic GPIO library. A "generic" GPIO
1199 implies configurability usually found on SoCs, particularly the
1200 ability to control internal pull resistors.
1202 config BOOTBLOCK_CUSTOM
1203 # To be selected by arch, SoC or mainboard if it does not want use the normal
1204 # src/lib/bootblock.c#main() C entry point.
1207 config MEMLAYOUT_LD_FILE
1209 default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
1211 This variable allows SoC/mainboard to supply in a custom linker file
1212 if required. This determines the linker file used for all the stages
1213 (bootblock, romstage, verstage, ramstage, postcar) in
1214 src/arch/${ARCH}/Makefile.inc.
1216 ###############################################################################
1217 # Set default values for symbols created before mainboards. This allows the
1218 # option to be displayed in the general menu, but the default to be loaded in
1219 # the mainboard if desired.
1220 config COMPRESS_RAMSTAGE
1221 default y if !UNCOMPRESSED_RAMSTAGE
1223 config COMPRESS_PRERAM_STAGES
1224 depends on !ARCH_X86
1227 config INCLUDE_CONFIG_FILE
1230 config BOOTSPLASH_FILE
1231 depends on BOOTSPLASH_IMAGE
1232 default "bootsplash.jpg"
1237 config HAVE_BOOTBLOCK
1241 config HAVE_VERSTAGE
1243 depends on VBOOT_SEPARATE_VERSTAGE
1246 config HAVE_ROMSTAGE
1250 config HAVE_RAMSTAGE
1252 default n if RAMPAYLOAD