2 * This file is part of the coreboot project.
4 * Copyright (C) 2013 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <console/console.h>
17 #include <device/device.h>
18 #include <device/pci.h>
19 #include <device/pciexp.h>
20 #include <device/pci_ids.h>
21 #include <reg_script.h>
23 #include <soc/pci_devs.h>
25 #include <soc/ramstage.h>
30 static int pll_en_off
;
31 static uint32_t strpfusecfg
;
33 static inline int root_port_offset(struct device
*dev
)
35 return PCI_FUNC(dev
->path
.pci
.devfn
);
38 static inline int is_first_port(struct device
*dev
)
40 return root_port_offset(dev
) == PCIE_PORT1_FUNC
;
43 static const struct reg_script init_static_before_exit_latency
[] = {
44 /* Disable optimized buffer flush fill and latency tolerant reporting */
45 REG_PCI_RMW32(DCAP2
, ~(OBFFS
| LTRMS
), 0),
46 REG_PCI_RMW32(DSTS2
, ~(OBFFEN
| LTRME
), 0),
47 /* Set maximum payload size. */
48 REG_PCI_RMW32(DCAP
, ~MPS_MASK
, 0),
49 /* Disable transmit datapath flush timer, clear transmit config change
50 * wait time, clear sideband interface idle counter. */
51 REG_PCI_RMW32(PHYCTL2_IOSFBCTL
, ~(TDFT
| TXCFGCHWAIT
| SIID
), 0),
55 static const struct reg_script init_static_after_exit_latency
[] = {
56 /* Set common clock configuration. */
57 REG_PCI_OR16(LCTL
, CCC
),
58 /* Set NFTS to 0x743a361b */
59 REG_PCI_WRITE32(NFTS
, 0x743a361b),
60 /* Set common clock latency to 0x3 */
61 REG_PCI_RMW32(MPC
, ~CCEL_MASK
, (0x3 << CCEL_SHIFT
)),
62 /* Set relay timer policy. */
63 REG_PCI_RMW32(RTP
, 0xff000000, 0x854c74),
64 /* Set IOSF packet fast transmit mode and link speed training policy. */
65 REG_PCI_OR16(MPC2
, IPF
| LSTP
),
66 /* Channel configuration - enable upstream posted split, set non-posted
67 * and posted request size */
68 REG_PCI_RMW32(CHCFG
, ~UPSD
, UNRS
| UPRS
),
69 /* Completion status replay enable and set TLP grant count */
70 REG_PCI_RMW32(CFG2
, ~(LATGC_MASK
), CSREN
| (3 << LATGC_SHIFT
)),
71 /* Assume no IOAPIC behind root port -- disable EOI forwarding. */
72 REG_PCI_OR16(MPC2
, EOIFD
),
74 REG_PCI_RMW32(AERCH
, ~0, (1 << 16) | (1 << 0)),
75 /* set completion timeout to 160ms to 170ms */
76 REG_PCI_RMW16(DSTS2
, ~CTD
, 0x6),
78 REG_PCI_OR16(DCTL_DSTS
, URE
| FEE
| NFE
| CEE
),
79 /* Read and write back capability registers. */
80 REG_PCI_OR32(0x34, 0),
81 REG_PCI_OR32(0x80, 0),
82 /* Retrain the link. */
83 REG_PCI_OR16(LCTL
, RL
),
87 static void byt_pcie_init(struct device
*dev
)
89 struct reg_script init_script
[] = {
90 REG_SCRIPT_NEXT(init_static_before_exit_latency
),
91 /* Exit latency configuration based on
92 * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/
93 REG_PCI_RMW32(LCAP
, ~L1EXIT_MASK
,
94 2 << (L1EXIT_SHIFT
+ pll_en_off
)),
95 REG_SCRIPT_NEXT(init_static_after_exit_latency
),
96 /* Disable hot plug, set power to 10W, set slot number. */
97 REG_PCI_RMW32(SLCAP
, ~(HPC
| HPS
),
98 (1 << SLS_SHIFT
) | (100 << SLV_SHIFT
) |
99 (root_port_offset(dev
) << SLN_SHIFT
)),
100 /* Dynamic clock gating. */
101 REG_PCI_OR32(RPPGEN
, RPDLCGEN
| RPDBCGEN
| RPSCGEN
),
102 REG_PCI_OR32(PWRCTL
, RPL1SQPOL
| RPDTSQPOL
),
103 REG_PCI_OR32(PCIEDBG
, SPCE
),
107 reg_script_run_on_dev(dev
, init_script
);
109 if (is_first_port(dev
)) {
110 struct soc_intel_baytrail_config
*config
= dev
->chip_info
;
111 uint32_t reg
= pci_read_config32(dev
, RPPGEN
);
112 reg
|= SRDLCGEN
| SRDBCGEN
;
114 if (config
&& config
->clkreq_enable
)
115 reg
|= LCLKREQEN
| BBCLKREQEN
;
117 pci_write_config32(dev
, RPPGEN
, reg
);
121 static const struct reg_script no_dev_behind_port
[] = {
122 REG_PCI_OR32(PCIEALC
, (1 << 26)),
123 REG_PCI_POLL32(PCIESTS1
, 0x1f000000, (1 << 24), 50000),
124 REG_PCI_OR32(PHYCTL4
, SQDIS
),
128 static void check_port_enabled(struct device
*dev
)
130 int rp_config
= (strpfusecfg
& LANECFG_MASK
) >> LANECFG_SHIFT
;
132 switch (root_port_offset(dev
)) {
133 case PCIE_PORT1_FUNC
:
134 /* Port 1 cannot be disabled from strapping config. */
136 case PCIE_PORT2_FUNC
:
137 /* Port 2 disabled in all configs but 4x1. */
138 if (rp_config
!= 0x0)
141 case PCIE_PORT3_FUNC
:
142 /* Port 3 disabled only in 1x4 config. */
143 if (rp_config
== 0x3)
146 case PCIE_PORT4_FUNC
:
147 /* Port 4 disabled in 1x4 and 2x2 config. */
148 if (rp_config
>= 0x2)
154 static u8
all_ports_no_dev_present(struct device
*dev
)
157 u8 temp
= dev
->path
.pci
.devfn
;
158 u8 device_not_present
= 1;
161 for (func
= 1; func
< PCIE_ROOT_PORT_COUNT
; func
++) {
162 dev
->path
.pci
.devfn
&= ~0x7;
163 dev
->path
.pci
.devfn
|= func
;
165 /* is pcie device there */
166 if (pci_read_config32(dev
, 0) == 0xFFFFFFFF)
169 data
= pci_read_config8(dev
, XCAP
+ 3) | (SI
>> 24);
170 pci_write_config8(dev
, XCAP
+ 3, data
);
172 /* is any device present */
173 if ((pci_read_config32(dev
, SLCTL_SLSTS
) & PDS
)) {
174 device_not_present
= 0;
179 dev
->path
.pci
.devfn
= temp
;
180 return device_not_present
;
183 static void check_device_present(struct device
*dev
)
185 /* Set slot implemented. */
186 pci_write_config32(dev
, XCAP
, pci_read_config32(dev
, XCAP
) | SI
);
188 /* No device present. */
189 if (!(pci_read_config32(dev
, SLCTL_SLSTS
) & PDS
)) {
190 printk(BIOS_DEBUG
, "No PCIe device present.\n");
191 if (is_first_port(dev
)) {
192 if (all_ports_no_dev_present(dev
)) {
193 reg_script_run_on_dev(dev
, no_dev_behind_port
);
197 reg_script_run_on_dev(dev
, no_dev_behind_port
);
200 } else if (!dev
->enabled
) {
201 /* Port is disabled, but device present. Disable link. */
202 pci_write_config32(dev
, LCTL
,
203 pci_read_config32(dev
, LCTL
) | LD
);
207 static void byt_pcie_enable(struct device
*dev
)
209 if (is_first_port(dev
)) {
210 struct soc_intel_baytrail_config
*config
= dev
->chip_info
;
211 uint32_t reg
= pci_read_config32(dev
, PHYCTL2_IOSFBCTL
);
212 pll_en_off
= !!(reg
& PLL_OFF_EN
);
214 strpfusecfg
= pci_read_config32(dev
, STRPFUSECFG
);
216 if (config
&& config
->pcie_wake_enable
)
217 southcluster_smm_save_param(
218 SMM_SAVE_PARAM_PCIE_WAKE_ENABLE
, 1);
221 /* Check if device is enabled in strapping. */
222 check_port_enabled(dev
);
223 /* Determine if device is behind port. */
224 check_device_present(dev
);
226 southcluster_enable_dev(dev
);
229 static void byt_pciexp_scan_bridge(struct device
*dev
)
231 static const struct reg_script wait_for_link_active
[] = {
232 REG_PCI_POLL32(LCTL
, (1 << 29) , (1 << 29), 50000),
236 /* wait for Link Active with 50ms timeout */
237 reg_script_run_on_dev(dev
, wait_for_link_active
);
239 do_pci_scan_bridge(dev
, pciexp_scan_bus
);
242 static void pcie_root_set_subsystem(struct device
*dev
, unsigned vid
,
245 uint32_t didvid
= ((did
& 0xffff) << 16) | (vid
& 0xffff);
248 didvid
= pci_read_config32(dev
, PCI_VENDOR_ID
);
249 pci_write_config32(dev
, 0x94, didvid
);
252 static struct pci_operations pcie_root_ops
= {
253 .set_subsystem
= &pcie_root_set_subsystem
,
256 static struct device_operations device_ops
= {
257 .read_resources
= pci_bus_read_resources
,
258 .set_resources
= pci_dev_set_resources
,
259 .enable_resources
= pci_bus_enable_resources
,
260 .init
= byt_pcie_init
,
261 .scan_bus
= byt_pciexp_scan_bridge
,
262 .enable
= byt_pcie_enable
,
263 .ops_pci
= &pcie_root_ops
,
266 static const unsigned short pci_device_ids
[] = {
267 PCIE_PORT1_DEVID
, PCIE_PORT2_DEVID
, PCIE_PORT3_DEVID
, PCIE_PORT4_DEVID
,
271 static const struct pci_driver pcie_root_ports __pci_driver
= {
273 .vendor
= PCI_VENDOR_ID_INTEL
,
274 .devices
= pci_device_ids
,