src/soc/intel/baytrail/northcluster.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <cpu/x86/smm.h>
  18 #include <device/device.h>
  19 #include <device/pci.h>
  20 #include <device/pci_ids.h>
  21 #include <vendorcode/google/chromeos/chromeos.h>
  22 #include <arch/acpi.h>
  23 #include <stddef.h>
  24 #include <soc/iomap.h>
  25 #include <soc/iosf.h>
  26 #include <soc/pci_devs.h>
  27 #include <soc/ramstage.h>
  28
  29 /* Host Memory Map:
  30  *
  31  * +--------------------------+ BMBOUND_HI
  32  * |     Usable DRAM          |
  33  * +--------------------------+ 4GiB
  34  * |     PCI Address Space    |
  35  * +--------------------------+ BMBOUND
  36  * |     TPM                  |
  37  * +--------------------------+ IMR2
  38  * |     TXE                  |
  39  * +--------------------------+ IMR1
  40  * |     iGD                  |
  41  * +--------------------------+
  42  * |     GTT                  |
  43  * +--------------------------+ SMMRRH, IRM0
  44  * |     TSEG                 |
  45  * +--------------------------+ SMMRRL
  46  * |     Usable DRAM          |
  47  * +--------------------------+ 0
  48  *
  49  * Note that there are really only a few regions that need to enumerated w.r.t.
  50  * coreboot's resource model:
  51  *
  52  * +--------------------------+ BMBOUND_HI
  53  * |     Cacheable/Usable     |
  54  * +--------------------------+ 4GiB
  55  *
  56  * +--------------------------+ BMBOUND
  57  * |    Uncacheable/Reserved  |
  58  * +--------------------------+ SMMRRH
  59  * |    Cacheable/Reserved    |
  60  * +--------------------------+ SMMRRL
  61  * |     Cacheable/Usable     |
  62  * +--------------------------+ 0
  63  */
  64 #define RES_IN_KiB(r) ((r) >> 10)
  65
  66 uint32_t nc_read_top_of_low_memory(void)
  67 {
  68         MAYBE_STATIC uint32_t tolm = 0;
  69
  70         if (tolm)
  71                 return tolm;
  72
  73         tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
  74
  75         return tolm;
  76 }
  77
  78 static void nc_read_resources(struct device *dev)
  79 {
  80         unsigned long mmconf;
  81         unsigned long bmbound;
  82         unsigned long bmbound_hi;
  83         unsigned long smmrrh;
  84         unsigned long smmrrl;
  85         unsigned long base_k, size_k;
  86         const unsigned long four_gig_kib = (4 << (30 - 10));
  87         int index = 0;
  88
  89         /* Read standard PCI resources. */
  90         pci_dev_read_resources(dev);
  91
  92         /* PCIe memory-mapped config space access - 256 MiB. */
  93         mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
  94         mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
  95
  96         /* 0 -> 0xa0000 */
  97         base_k = RES_IN_KiB(0);
  98         size_k = RES_IN_KiB(0xa0000) - base_k;
  99         ram_resource(dev, index++, base_k, size_k);
 100
 101         /* The SMMRR registers are 1MiB granularity with smmrrh being
 102          * inclusive of the SMM region. */
 103         smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10;
 104         smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10;
 105
 106         /* 0xc0000 -> smrrl - cacheable and usable */
 107         base_k = RES_IN_KiB(0xc0000);
 108         size_k = smmrrl - base_k;
 109         ram_resource(dev, index++, base_k, size_k);
 110
 111         if (smmrrh > smmrrl)
 112                 reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl);
 113
 114         /* All address space between bmbound and smmrrh is unusable. */
 115         bmbound = RES_IN_KiB(nc_read_top_of_low_memory());
 116         mmio_resource(dev, index++, smmrrh, bmbound - smmrrh);
 117
 118         /* The BMBOUND_HI register matches register bits of 31:24 with address
 119          * bits of 35:28. Therefore, shift register to align properly. */
 120         bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
 121         bmbound_hi = RES_IN_KiB(bmbound_hi) << 4;
 122         if (bmbound_hi > four_gig_kib)
 123                 ram_resource(dev, index++, four_gig_kib,
 124                              bmbound_hi - four_gig_kib);
 125
 126         /* Reserve everything between A segment and 1MB:
 127          *
 128          * 0xa0000 - 0xbffff: legacy VGA
 129          * 0xc0000 - 0xfffff: RAM
 130          */
 131         mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
 132         reserved_ram_resource(dev, index++, (0xc0000 >> 10),
 133                               (0x100000 - 0xc0000) >> 10);
 134
 135         chromeos_reserve_ram_oops(dev, index++);
 136 }
 137
 138 static struct device_operations nc_ops = {
 139         .read_resources   = nc_read_resources,
 140         .acpi_fill_ssdt_generator = generate_cpu_entries,
 141         .set_resources    = NULL,
 142         .enable_resources = NULL,
 143         .init             = NULL,
 144         .enable           = NULL,
 145         .scan_bus         = NULL,
 146         .ops_pci          = &soc_pci_ops,
 147 };
 148
 149 static const struct pci_driver nc_driver __pci_driver = {
 150         .ops    = &nc_ops,
 151         .vendor = PCI_VENDOR_ID_INTEL,
 152         .device = SOC_DEVID,
 153 };