src/soc/intel/baytrail/emmc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <arch/io.h>
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <reg_script.h>
  23
  24 #include <soc/iosf.h>
  25 #include <soc/nvs.h>
  26 #include <soc/pci_devs.h>
  27 #include <soc/ramstage.h>
  28 #include "chip.h"
  29
  30 static const struct reg_script emmc_ops[] = {
  31         /* Enable 2ms card stable feature. */
  32         REG_PCI_OR32(0xa8, (1 << 24)),
  33         /* Enable HS200 */
  34         REG_PCI_WRITE32(0xa0, 0x446cc801),
  35         REG_PCI_WRITE32(0xa4, 0x80000807),
  36         /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */
  37         REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
  38         /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en  = 1 */
  39         REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
  40         /* Set slew for HS200 */
  41         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
  42         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
  43         /* Max timeout */
  44         REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e),
  45         REG_SCRIPT_END,
  46 };
  47
  48 static void emmc_init(struct device *dev)
  49 {
  50         struct soc_intel_baytrail_config *config = dev->chip_info;
  51
  52         printk(BIOS_DEBUG, "eMMC init\n");
  53         reg_script_run_on_dev(dev, emmc_ops);
  54
  55         if (config->scc_acpi_mode)
  56                 scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC);
  57 }
  58
  59 static struct device_operations device_ops = {
  60         .read_resources         = pci_dev_read_resources,
  61         .set_resources          = pci_dev_set_resources,
  62         .enable_resources       = pci_dev_enable_resources,
  63         .init                   = emmc_init,
  64         .enable                 = NULL,
  65         .scan_bus               = NULL,
  66         .ops_pci                = &soc_pci_ops,
  67 };
  68
  69 static const struct pci_driver southcluster __pci_driver = {
  70         .ops            = &device_ops,
  71         .vendor         = PCI_VENDOR_ID_INTEL,
  72         .device         = MMC_DEVID,
  73 };