2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/acpi.h>
26 #include <cpu/intel/haswell/haswell.h>
27 #include <cpu/x86/msr.h>
28 #include <device/device.h>
29 #include <device/pci.h>
30 #include <device/pci_ids.h>
31 #include <device/hypertransport.h>
35 #include <cpu/x86/smm.h>
36 #include <boot/tables.h>
41 static int bridge_revision_id
= -1;
43 int bridge_silicon_revision(void)
45 if (bridge_revision_id
< 0) {
46 uint8_t stepping
= cpuid_eax(1) & 0xf;
47 uint8_t bridge_id
= pci_read_config16(
48 dev_find_slot(0, PCI_DEVFN(0, 0)),
49 PCI_DEVICE_ID
) & 0xf0;
50 bridge_revision_id
= bridge_id
| stepping
;
52 return bridge_revision_id
;
55 /* Reserve everything between A segment and 1MB:
57 * 0xa0000 - 0xbffff: legacy VGA
58 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
59 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
61 static const int legacy_hole_base_k
= 0xa0000 / 1024;
62 static const int legacy_hole_size_k
= 384;
64 void cbmem_post_handling(void)
69 static int get_pcie_bar(device_t dev
, unsigned int index
, u32
*base
, u32
*len
)
76 pciexbar_reg
= pci_read_config32(dev
, index
);
78 if (!(pciexbar_reg
& (1 << 0)))
81 switch ((pciexbar_reg
>> 1) & 3) {
83 *base
= pciexbar_reg
& ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
84 *len
= 256 * 1024 * 1024;
87 *base
= pciexbar_reg
& ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
88 *len
= 128 * 1024 * 1024;
91 *base
= pciexbar_reg
& ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
92 *len
= 64 * 1024 * 1024;
99 static void pci_domain_set_resources(device_t dev
)
101 assign_resources(dev
->link_list
);
104 /* TODO We could determine how many PCIe busses we need in
105 * the bar. For now that number is hardcoded to a max of 64.
106 * See e7525/northbridge.c for an example.
108 static struct device_operations pci_domain_ops
= {
109 .read_resources
= pci_domain_read_resources
,
110 .set_resources
= pci_domain_set_resources
,
111 .enable_resources
= NULL
,
113 .scan_bus
= pci_domain_scan_bus
,
114 #if CONFIG_MMCONF_SUPPORT_DEFAULT
115 .ops_pci_bus
= &pci_ops_mmconf
,
117 .ops_pci_bus
= &pci_cf8_conf1
,
121 static int get_bar(device_t dev
, unsigned int index
, u32
*base
, u32
*len
)
125 bar
= pci_read_config32(dev
, index
);
127 /* If not enabled don't report it. */
131 /* Knock down the enable bit. */
137 /* There are special BARs that actually are programmed in the MCHBAR. These
138 * Intel special features, but they do consume resources that need to be
140 static int get_bar_in_mchbar(device_t dev
, unsigned int index
, u32
*base
,
145 bar
= MCHBAR32(index
);
147 /* If not enabled don't report it. */
151 /* Knock down the enable bit. */
157 struct fixed_mmio_descriptor
{
160 int (*get_resource
)(device_t dev
, unsigned int index
,
161 u32
*base
, u32
*size
);
162 const char *description
;
165 #define SIZE_KB(x) ((x)*1024)
166 struct fixed_mmio_descriptor mc_fixed_resources
[] = {
167 { PCIEXBAR
, SIZE_KB(0), get_pcie_bar
, "PCIEXBAR" },
168 { MCHBAR
, SIZE_KB(32), get_bar
, "MCHBAR" },
169 { DMIBAR
, SIZE_KB(4), get_bar
, "DMIBAR" },
170 { EPBAR
, SIZE_KB(4), get_bar
, "EPBAR" },
171 { 0x5420, SIZE_KB(4), get_bar_in_mchbar
, "GDXCBAR" },
172 { 0x5408, SIZE_KB(16), get_bar_in_mchbar
, "EDRAMBAR" },
177 * Add all known fixed MMIO ranges that hang off the host bridge/memory
180 static void mc_add_fixed_mmio_resources(device_t dev
)
184 for (i
= 0; i
< ARRAY_SIZE(mc_fixed_resources
); i
++) {
187 struct resource
*resource
;
190 size
= mc_fixed_resources
[i
].size
;
191 index
= mc_fixed_resources
[i
].index
;
192 if (!mc_fixed_resources
[i
].get_resource(dev
, index
,
196 resource
= new_resource(dev
, mc_fixed_resources
[i
].index
);
197 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_FIXED
|
198 IORESOURCE_STORED
| IORESOURCE_RESERVE
|
200 resource
->base
= base
;
201 resource
->size
= size
;
202 printk(BIOS_DEBUG
, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
203 __func__
, mc_fixed_resources
[i
].description
, index
,
204 (unsigned long)base
, (unsigned long)(base
+ size
- 1));
210 * +--------------------------+ TOUUD
212 * +--------------------------+ 4GiB
213 * | PCI Address Space |
214 * +--------------------------+ TOLUD (also maps into MC address space)
216 * +--------------------------+ BDSM
218 * +--------------------------+ BGSM
220 * +--------------------------+ TSEGMB
222 * +--------------------------+ 0
224 * Some of the base registers above can be equal making the size of those
225 * regions 0. The reason is because the memory controller internally subtracts
226 * the base registers from each other to determine sizes of the regions. In
227 * other words, the memory map is in a fixed order no matter what.
234 const char *description
;
237 static void read_map_entry(device_t dev
, struct map_entry
*entry
,
243 /* All registers are on a 1MiB granularity. */
244 mask
= ((1ULL<<20)-1);
249 if (entry
->is_64_bit
) {
250 value
= pci_read_config32(dev
, entry
->reg
+ 4);
254 value
|= pci_read_config32(dev
, entry
->reg
);
263 #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
266 .is_64_bit = is_64_, \
267 .is_limit = is_limit_, \
268 .description = desc_, \
271 #define MAP_ENTRY_BASE_64(reg_, desc_) \
272 MAP_ENTRY(reg_, 1, 0, desc_)
273 #define MAP_ENTRY_LIMIT_64(reg_, desc_) \
274 MAP_ENTRY(reg_, 1, 1, desc_)
275 #define MAP_ENTRY_BASE_32(reg_, desc_) \
276 MAP_ENTRY(reg_, 0, 0, desc_)
293 static struct map_entry memory_map
[NUM_MAP_ENTRIES
] = {
294 [TOM_REG
] = MAP_ENTRY_BASE_64(TOM
, "TOM"),
295 [TOUUD_REG
] = MAP_ENTRY_BASE_64(TOUUD
, "TOUUD"),
296 [MESEG_BASE_REG
] = MAP_ENTRY_BASE_64(MESEG_BASE
, "MESEG_BASE"),
297 [MESEG_LIMIT_REG
] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT
, "MESEG_LIMIT"),
298 [REMAP_BASE_REG
] = MAP_ENTRY_BASE_64(REMAPBASE
, "REMAP_BASE"),
299 [REMAP_LIMIT_REG
] = MAP_ENTRY_LIMIT_64(REMAPLIMIT
, "REMAP_LIMIT"),
300 [TOLUD_REG
] = MAP_ENTRY_BASE_32(TOLUD
, "TOLUD"),
301 [BDSM_REG
] = MAP_ENTRY_BASE_32(BDSM
, "BDSM"),
302 [BGSM_REG
] = MAP_ENTRY_BASE_32(BGSM
, "BGSM"),
303 [TSEG_REG
] = MAP_ENTRY_BASE_32(TSEG
, "TESGMB"),
306 static void mc_read_map_entries(device_t dev
, uint64_t *values
)
309 for (i
= 0; i
< NUM_MAP_ENTRIES
; i
++) {
310 read_map_entry(dev
, &memory_map
[i
], &values
[i
]);
314 static void mc_report_map_entries(device_t dev
, uint64_t *values
)
317 for (i
= 0; i
< NUM_MAP_ENTRIES
; i
++) {
318 printk(BIOS_DEBUG
, "MC MAP: %s: 0x%llx\n",
319 memory_map
[i
].description
, values
[i
]);
321 /* One can validate the BDSM and BGSM against the GGC. */
322 printk(BIOS_DEBUG
, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev
, GGC
));
325 static void mc_add_dram_resources(device_t dev
)
327 unsigned long base_k
, size_k
;
329 struct resource
*resource
;
330 uint64_t mc_values
[NUM_MAP_ENTRIES
];
332 /* Read in the MAP registers and report their values. */
333 mc_read_map_entries(dev
, &mc_values
[0]);
334 mc_report_map_entries(dev
, &mc_values
[0]);
337 * These are the host memory ranges that should be added:
338 * - 0 -> SMM_DEFAULT_BASE : cacheable
339 * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE :
340 * cacheable and reserved
341 * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable
342 * - 0xc0000 -> TSEG : cacheable
343 * - TESG -> TOLUD: not cacheable with standard MTRRs and reserved
344 * - 4GiB -> TOUUD: cacheable
346 * The default SMRAM space is reserved so that the range doesn't
347 * have to be saved during S3 Resume. Once marked reserved the OS
348 * cannot use the memory. This is a bit of an odd place to reserve
349 * the region, but the CPU devices don't have dev_ops->read_resources()
352 * The range 0xa0000 -> 0xc0000 does not have any resources
353 * associated with it to handle legacy VGA memory. If this range
354 * is not omitted the mtrr code will setup the area as cacheable
355 * causing VGA access to not work.
357 * It should be noted that cacheable entry types need to be added in
358 * order. The reason is that the current MTRR code assumes this and
359 * falls over itself if it isn't.
361 * The resource index starts low and should not meet or exceed
362 * PCI_BASE_ADDRESS_0.
366 /* 0 - > SMM_DEFAULT_BASE */
368 size_k
= SMM_DEFAULT_BASE
>> 10;
369 ram_resource(dev
, index
++, base_k
, size_k
);
371 /* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */
372 resource
= new_resource(dev
, index
++);
373 resource
->base
= SMM_DEFAULT_BASE
;
374 resource
->size
= SMM_DEFAULT_SIZE
;
375 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_FIXED
|
376 IORESOURCE_CACHEABLE
| IORESOURCE_STORED
|
377 IORESOURCE_RESERVE
| IORESOURCE_ASSIGNED
;
379 /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */
380 base_k
= (SMM_DEFAULT_BASE
+ SMM_DEFAULT_SIZE
) >> 10;
381 size_k
= (0xa0000 >> 10) - base_k
;
382 ram_resource(dev
, index
++, base_k
, size_k
);
384 /* 0xc0000 -> TSEG */
385 base_k
= 0xc0000 >> 10;
386 size_k
= (unsigned long)(mc_values
[TSEG_REG
] >> 10) - base_k
;
387 ram_resource(dev
, index
++, base_k
, size_k
);
390 resource
= new_resource(dev
, index
++);
391 resource
->base
= mc_values
[TSEG_REG
];
392 resource
->size
= mc_values
[TOLUD_REG
] - resource
->base
;
393 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_FIXED
|
394 IORESOURCE_STORED
| IORESOURCE_RESERVE
|
398 base_k
= 4096 * 1024; /* 4GiB */
399 size_k
= (unsigned long)(mc_values
[TOUUD_REG
] >> 10) - base_k
;
400 ram_resource(dev
, index
++, base_k
, size_k
);
402 mmio_resource(dev
, index
++, legacy_hole_base_k
, legacy_hole_size_k
);
403 #if CONFIG_CHROMEOS_RAMOOPS
404 mmio_resource(dev
, index
++, CONFIG_CHROMEOS_RAMOOPS_RAM_START
>> 10,
405 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE
>> 10);
408 /* Leave some space for ACPI, PIRQ and MP tables */
409 high_tables_size
= HIGH_MEMORY_SIZE
;
410 high_tables_base
= mc_values
[TSEG_REG
] - high_tables_size
;
413 static void mc_read_resources(device_t dev
)
415 /* Read standard PCI resources. */
416 pci_dev_read_resources(dev
);
418 /* Add all fixed MMIO resources. */
419 mc_add_fixed_mmio_resources(dev
);
421 /* Calculate and add DRAM resources. */
422 mc_add_dram_resources(dev
);
425 static void intel_set_subsystem(device_t dev
, unsigned vendor
, unsigned device
)
427 if (!vendor
|| !device
) {
428 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
429 pci_read_config32(dev
, PCI_VENDOR_ID
));
431 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
432 ((device
& 0xffff) << 16) | (vendor
& 0xffff));
436 static void northbridge_dmi_init(struct device
*dev
)
440 /* Clear error status bits */
441 DMIBAR32(0x1c4) = 0xffffffff;
442 DMIBAR32(0x1d0) = 0xffffffff;
444 /* Steps prior to DMI ASPM */
445 if ((bridge_silicon_revision() & BASE_REV_MASK
) == BASE_REV_SNB
) {
446 reg32
= DMIBAR32(0x250);
447 reg32
&= ~((1 << 22)|(1 << 20));
449 DMIBAR32(0x250) = reg32
;
452 reg32
= DMIBAR32(0x238);
454 DMIBAR32(0x238) = reg32
;
456 if (bridge_silicon_revision() >= SNB_STEP_D0
) {
457 reg32
= DMIBAR32(0x1f8);
459 DMIBAR32(0x1f8) = reg32
;
460 } else if (bridge_silicon_revision() >= SNB_STEP_D1
) {
461 reg32
= DMIBAR32(0x1f8);
464 DMIBAR32(0x1f8) = reg32
;
466 reg32
= DMIBAR32(0x1fc);
467 reg32
|= (1 << 12) | (1 << 23);
468 DMIBAR32(0x1fc) = reg32
;
471 /* Enable ASPM on SNB link, should happen before PCH link */
472 if ((bridge_silicon_revision() & BASE_REV_MASK
) == BASE_REV_SNB
) {
473 reg32
= DMIBAR32(0xd04);
475 DMIBAR32(0xd04) = reg32
;
478 reg32
= DMIBAR32(0x88);
479 reg32
|= (1 << 1) | (1 << 0);
480 DMIBAR32(0x88) = reg32
;
483 static void northbridge_init(struct device
*dev
)
488 northbridge_dmi_init(dev
);
490 bridge_type
= MCHBAR32(0x5f10);
491 bridge_type
&= ~0xff;
493 if ((bridge_silicon_revision() & BASE_REV_MASK
) == BASE_REV_IVB
) {
494 /* Enable Power Aware Interrupt Routing */
495 u8 pair
= MCHBAR8(0x5418);
496 pair
&= ~0xf; /* Clear 3:0 */
497 pair
|= 0x4; /* Fixed Priority */
498 MCHBAR8(0x5418) = pair
;
500 /* 30h for IvyBridge */
503 /* 20h for Sandybridge */
506 MCHBAR32(0x5f10) = bridge_type
;
509 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
510 * that BIOS has initialized memory and power management
512 bios_reset_cpl
= MCHBAR8(BIOS_RESET_CPL
);
514 MCHBAR8(BIOS_RESET_CPL
) = bios_reset_cpl
;
515 printk(BIOS_DEBUG
, "Set BIOS_RESET_CPL\n");
517 /* Configure turbo power limits 1ms after reset complete bit */
519 set_power_limits(28);
522 * CPUs with configurable TDP also need power limits set
523 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
525 if (cpu_config_tdp_levels()) {
526 msr_t msr
= rdmsr(MSR_PKG_POWER_LIMIT
);
527 MCHBAR32(0x59A0) = msr
.lo
;
528 MCHBAR32(0x59A4) = msr
.hi
;
531 /* Set here before graphics PM init */
532 MCHBAR32(0x5500) = 0x00100001;
535 static void northbridge_enable(device_t dev
)
537 #if CONFIG_HAVE_ACPI_RESUME
538 switch (pci_read_config32(dev
, SKPAD
)) {
540 printk(BIOS_DEBUG
, "Normal boot.\n");
544 printk(BIOS_DEBUG
, "S3 Resume.\n");
548 printk(BIOS_DEBUG
, "Unknown boot method, assuming normal.\n");
555 static struct pci_operations intel_pci_ops
= {
556 .set_subsystem
= intel_set_subsystem
,
559 static struct device_operations mc_ops
= {
560 .read_resources
= mc_read_resources
,
561 .set_resources
= pci_dev_set_resources
,
562 .enable_resources
= pci_dev_enable_resources
,
563 .init
= northbridge_init
,
564 .enable
= northbridge_enable
,
566 .ops_pci
= &intel_pci_ops
,
569 static const struct pci_driver mc_driver_hsw_mobile __pci_driver
= {
571 .vendor
= PCI_VENDOR_ID_INTEL
,
572 .device
= 0x0c04, /* Mobile Haswell */
575 static const struct pci_driver mc_driver_hsw_ult __pci_driver
= {
577 .vendor
= PCI_VENDOR_ID_INTEL
,
578 .device
= 0x0a04, /* ULT Haswell */
581 static void cpu_bus_init(device_t dev
)
583 initialize_cpus(dev
->link_list
);
586 static void cpu_bus_noop(device_t dev
)
590 static struct device_operations cpu_bus_ops
= {
591 .read_resources
= cpu_bus_noop
,
592 .set_resources
= cpu_bus_noop
,
593 .enable_resources
= cpu_bus_noop
,
594 .init
= cpu_bus_init
,
598 static void enable_dev(device_t dev
)
600 /* Set the operations if it is a special bus type */
601 if (dev
->path
.type
== DEVICE_PATH_DOMAIN
) {
602 dev
->ops
= &pci_domain_ops
;
603 } else if (dev
->path
.type
== DEVICE_PATH_CPU_CLUSTER
) {
604 dev
->ops
= &cpu_bus_ops
;
608 struct chip_operations northbridge_intel_haswell_ops
= {
609 CHIP_NAME("Intel i7 (Haswell) integrated Northbridge")
610 .enable_dev
= enable_dev
,