src/soc/intel/alderlake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <device/mmio.h>
   7 #include <arch/smp/mpspec.h>
   8 #include <console/console.h>
   9 #include <device/device.h>
  10 #include <device/pci_ops.h>
  11 #include <intelblocks/cpulib.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelblocks/acpi.h>
  14 #include <soc/cpu.h>
  15 #include <soc/iomap.h>
  16 #include <soc/nvs.h>
  17 #include <soc/pci_devs.h>
  18 #include <soc/pm.h>
  19 #include <soc/soc_chip.h>
  20 #include <soc/systemagent.h>
  21 #include <string.h>
  22 #include <types.h>
  23
  24 /*
  25  * List of supported C-states in this processor.
  26  */
  27 enum {
  28         C_STATE_C0,             /* 0 */
  29         C_STATE_C1,             /* 1 */
  30         C_STATE_C1E,            /* 2 */
  31         C_STATE_C6_SHORT_LAT,   /* 3 */
  32         C_STATE_C6_LONG_LAT,    /* 4 */
  33         C_STATE_C7_SHORT_LAT,   /* 5 */
  34         C_STATE_C7_LONG_LAT,    /* 6 */
  35         C_STATE_C7S_SHORT_LAT,  /* 7 */
  36         C_STATE_C7S_LONG_LAT,   /* 8 */
  37         C_STATE_C8,             /* 9 */
  38         C_STATE_C9,             /* 10 */
  39         C_STATE_C10,            /* 11 */
  40         NUM_C_STATES
  41 };
  42
  43 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  44         [C_STATE_C0] = {},
  45         [C_STATE_C1] = {
  46                 .latency = C1_LATENCY,
  47                 .power = C1_POWER,
  48                 .resource = MWAIT_RES(0, 0),
  49         },
  50         [C_STATE_C1E] = {
  51                 .latency = C1_LATENCY,
  52                 .power = C1_POWER,
  53                 .resource = MWAIT_RES(0, 1),
  54         },
  55         [C_STATE_C6_SHORT_LAT] = {
  56                 .latency = C6_LATENCY,
  57                 .power = C6_POWER,
  58                 .resource = MWAIT_RES(2, 0),
  59         },
  60         [C_STATE_C6_LONG_LAT] = {
  61                 .latency = C6_LATENCY,
  62                 .power = C6_POWER,
  63                 .resource = MWAIT_RES(2, 1),
  64         },
  65         [C_STATE_C7_SHORT_LAT] = {
  66                 .latency = C7_LATENCY,
  67                 .power = C7_POWER,
  68                 .resource = MWAIT_RES(3, 0),
  69         },
  70         [C_STATE_C7_LONG_LAT] = {
  71                 .latency = C7_LATENCY,
  72                 .power = C7_POWER,
  73                 .resource = MWAIT_RES(3, 1),
  74         },
  75         [C_STATE_C7S_SHORT_LAT] = {
  76                 .latency = C7_LATENCY,
  77                 .power = C7_POWER,
  78                 .resource = MWAIT_RES(3, 2),
  79         },
  80         [C_STATE_C7S_LONG_LAT] = {
  81                 .latency = C7_LATENCY,
  82                 .power = C7_POWER,
  83                 .resource = MWAIT_RES(3, 3),
  84         },
  85         [C_STATE_C8] = {
  86                 .latency = C8_LATENCY,
  87                 .power = C8_POWER,
  88                 .resource = MWAIT_RES(4, 0),
  89         },
  90         [C_STATE_C9] = {
  91                 .latency = C9_LATENCY,
  92                 .power = C9_POWER,
  93                 .resource = MWAIT_RES(5, 0),
  94         },
  95         [C_STATE_C10] = {
  96                 .latency = C10_LATENCY,
  97                 .power = C10_POWER,
  98                 .resource = MWAIT_RES(6, 0),
  99         },
 100 };
 101
 102 static int cstate_set_non_s0ix[] = {
 103         C_STATE_C1,
 104         C_STATE_C6_LONG_LAT,
 105         C_STATE_C7S_LONG_LAT
 106 };
 107
 108 static int cstate_set_s0ix[] = {
 109         C_STATE_C1,
 110         C_STATE_C6_LONG_LAT,
 111         C_STATE_C10
 112 };
 113
 114 acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 115 {
 116         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 117                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 118         int *set;
 119         int i;
 120
 121         config_t *config = config_of_soc();
 122
 123         int is_s0ix_enable = config->s0ix_enable;
 124
 125         if (is_s0ix_enable) {
 126                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 127                 set = cstate_set_s0ix;
 128         } else {
 129                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 130                 set = cstate_set_non_s0ix;
 131         }
 132
 133         for (i = 0; i < *entries; i++) {
 134                 map[i] = cstate_map[set[i]];
 135                 map[i].ctype = i + 1;
 136         }
 137         return map;
 138 }
 139
 140 void soc_power_states_generation(int core_id, int cores_per_package)
 141 {
 142         config_t *config = config_of_soc();
 143
 144         if (config->eist_enable)
 145                 /* Generate P-state tables */
 146                 generate_p_state_entries(core_id, cores_per_package);
 147 }
 148
 149 void soc_fill_fadt(acpi_fadt_t *fadt)
 150 {
 151         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 152
 153         config_t *config = config_of_soc();
 154
 155         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 156         fadt->pm_tmr_len = 4;
 157         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 158         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 159         fadt->x_pm_tmr_blk.bit_offset = 0;
 160         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 161         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 162         fadt->x_pm_tmr_blk.addrh = 0x0;
 163
 164         if (config->s0ix_enable)
 165                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 166 }
 167
 168 uint32_t soc_read_sci_irq_select(void)
 169 {
 170         return read32p(soc_read_pmc_base() + IRQ_REG);
 171 }
 172
 173 static unsigned long soc_fill_dmar(unsigned long current)
 174 {
 175         const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 176         const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 177
 178         if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
 179                 const unsigned long tmp = current;
 180
 181                 current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 182                 current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
 183
 184                 acpi_dmar_drhd_fixup(tmp, current);
 185         }
 186
 187         const uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 188         const bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 189
 190         if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
 191                 const unsigned long tmp = current;
 192
 193                 current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
 194                 current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0);
 195
 196                 acpi_dmar_drhd_fixup(tmp, current);
 197         }
 198
 199         /* TCSS Thunderbolt root ports */
 200         for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
 201                 if (is_devfn_enabled(SA_DEVFN_TBT(i))) {
 202                         const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK;
 203                         const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED;
 204                         if (tbtbar && tbten) {
 205                                 const unsigned long tmp = current;
 206
 207                                 current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
 208                                 current += acpi_create_dmar_ds_pci_br(current, 0,
 209                                                                       SA_DEV_SLOT_TBT, i);
 210
 211                                 acpi_dmar_drhd_fixup(tmp, current);
 212                         }
 213                 }
 214         }
 215
 216         const uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
 217         const bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
 218
 219         if (vtvc0bar && vtvc0en) {
 220                 const unsigned long tmp = current;
 221
 222                 current += acpi_create_dmar_drhd(current,
 223                                 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
 224                 current += acpi_create_dmar_ds_ioapic(current,
 225                                 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
 226                                 V_P2SB_CFG_IBDF_FUNC);
 227                 current += acpi_create_dmar_ds_msi_hpet(current,
 228                                 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
 229                                 V_P2SB_CFG_HBDF_FUNC);
 230
 231                 acpi_dmar_drhd_fixup(tmp, current);
 232         }
 233
 234         /* Add RMRR entry */
 235         if (is_devfn_enabled(SA_DEVFN_IGD)) {
 236                 const unsigned long tmp = current;
 237                 current += acpi_create_dmar_rmrr(current, 0,
 238                                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 239                 current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
 240                 acpi_dmar_rmrr_fixup(tmp, current);
 241         }
 242
 243         return current;
 244 }
 245
 246 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
 247                                    struct acpi_rsdp *rsdp)
 248 {
 249         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 250
 251         /*
 252          * Create DMAR table only if we have VT-d capability and FSP does not override its
 253          * feature.
 254          */
 255         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 256             !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
 257                 return current;
 258
 259         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 260         acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
 261         current += dmar->header.length;
 262         current = acpi_align_current(current);
 263         acpi_add_table(rsdp, dmar);
 264
 265         return current;
 266 }
 267
 268 void soc_fill_gnvs(struct global_nvs *gnvs)
 269 {
 270         config_t *config = config_of_soc();
 271
 272         /* Enable DPTF based on mainboard configuration */
 273         gnvs->dpte = config->dptf_enable;
 274
 275         /* Set USB2/USB3 wake enable bitmaps. */
 276         gnvs->u2we = config->usb2_wake_enable_bitmap;
 277         gnvs->u3we = config->usb3_wake_enable_bitmap;
 278
 279         /* Fill in Above 4GB MMIO resource */
 280         sa_fill_gnvs(gnvs);
 281 }
 282
 283 int soc_madt_sci_irq_polarity(int sci)
 284 {
 285         return MP_IRQ_POLARITY_HIGH;
 286 }