2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <cpu/x86/tsc.h>
18 #include <cpu/x86/msr.h>
19 #include <cpu/intel/speedstep.h>
23 * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
25 static void _udelay(const u32 us
, const u32 numerator
, const int total
)
28 tsc_t tsc
, tsc1
, tscd
;
31 u32 d
; /* ticks per us */
33 msr
= rdmsr(MSR_FSB_FREQ
);
34 switch (msr
.lo
& 0x07) {
59 divisor
= (msr
.hi
>> 8) & 0x1f;
61 d
= ((fsb
* divisor
) / numerator
) / 4; /* CPU clock is always a quarter. */
63 multiply_to_tsc(&tscd
, us
, d
);
67 dword
= tsc1
.lo
+ tscd
.lo
;
68 if ((dword
< tsc1
.lo
) || (dword
< tscd
.lo
)) {
79 } while ((tsc
.hi
< tsc1
.hi
)
80 || ((tsc
.hi
== tsc1
.hi
) && (tsc
.lo
< tsc1
.lo
)));
83 void udelay(const u32 us
)