src/soc/intel/icelake/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <fsp/api.h>
   7 #include <fsp/util.h>
   8 #include <intelblocks/lpss.h>
   9 #include <intelblocks/xdci.h>
  10 #include <soc/intel/common/vbt.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/ramstage.h>
  13 #include <soc/soc_chip.h>
  14 #include <string.h>
  15 #include <intelblocks/mp_init.h>
  16 #include <fsp/ppi/mp_service_ppi.h>
  17
  18 static void parse_devicetree(FSP_S_CONFIG *params)
  19 {
  20         const struct soc_intel_icelake_config *config;
  21         config = config_of_soc();
  22
  23         for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
  24                 params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
  25
  26         for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
  27                 params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
  28                 params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
  29                 params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
  30         }
  31
  32         for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
  33                 params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
  34 }
  35
  36 /* UPD parameters to be initialized before SiliconInit */
  37 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
  38 {
  39         int i;
  40         FSP_S_CONFIG *params = &supd->FspsConfig;
  41
  42         struct soc_intel_icelake_config *config;
  43         config = config_of_soc();
  44
  45         /* Parse device tree and enable/disable devices */
  46         parse_devicetree(params);
  47
  48         /* Load VBT before devicetree-specific config. */
  49         params->GraphicsConfigPtr = (uintptr_t)vbt_get();
  50
  51         /* Use coreboot MP PPI services if Kconfig is enabled */
  52         if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
  53                 params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
  54
  55         mainboard_silicon_init_params(params);
  56
  57         params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
  58
  59         params->PavpEnable = CONFIG(PAVP);
  60
  61         /* Unlock upper 8 bytes of RTC RAM */
  62         params->PchLockDownRtcMemoryLock = 0;
  63
  64         params->CnviBtAudioOffload = config->CnviBtAudioOffload;
  65         /* SATA */
  66         params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
  67         if (params->SataEnable) {
  68                 params->SataMode = config->SataMode;
  69                 params->SataSalpSupport = config->SataSalpSupport;
  70                 memcpy(params->SataPortsEnable, config->SataPortsEnable,
  71                                 sizeof(params->SataPortsEnable));
  72                 memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
  73                                 sizeof(params->SataPortsDevSlp));
  74         }
  75
  76         /* Lan */
  77         params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
  78
  79         /* Audio */
  80         params->PchHdaDspEnable = config->PchHdaDspEnable;
  81         params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
  82         params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
  83         params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
  84         params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
  85         params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
  86         params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
  87         params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
  88         params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
  89         params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
  90         params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
  91
  92         /* disable Legacy PME */
  93         memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
  94
  95         /* Legacy 8254 timer support */
  96         params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
  97         params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
  98
  99         /* S0ix */
 100         params->PchPmSlpS0Enable = config->s0ix_enable;
 101
 102         /* USB */
 103         for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 104                 params->PortUsb20Enable[i] =
 105                         config->usb2_ports[i].enable;
 106                 params->Usb2PhyPetxiset[i] =
 107                         config->usb2_ports[i].pre_emp_bias;
 108                 params->Usb2PhyTxiset[i] =
 109                         config->usb2_ports[i].tx_bias;
 110                 params->Usb2PhyPredeemp[i] =
 111                         config->usb2_ports[i].tx_emp_enable;
 112                 params->Usb2PhyPehalfbit[i] =
 113                         config->usb2_ports[i].pre_emp_bit;
 114
 115                 if (config->usb2_ports[i].enable)
 116                         params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
 117                 else
 118                         params->Usb2OverCurrentPin[i] = 0xff;
 119         }
 120
 121         for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 122                 params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 123                 if (config->usb3_ports[i].enable) {
 124                         params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 125                 } else {
 126                         params->Usb3OverCurrentPin[i] = 0xff;
 127                 }
 128                 if (config->usb3_ports[i].tx_de_emp) {
 129                         params->Usb3HsioTxDeEmphEnable[i] = 1;
 130                         params->Usb3HsioTxDeEmph[i] =
 131                                 config->usb3_ports[i].tx_de_emp;
 132                 }
 133                 if (config->usb3_ports[i].tx_downscale_amp) {
 134                         params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
 135                         params->Usb3HsioTxDownscaleAmp[i] =
 136                                 config->usb3_ports[i].tx_downscale_amp;
 137                 }
 138         }
 139
 140         /* Enable xDCI controller if enabled in devicetree and allowed */
 141         if (!xdci_can_enable())
 142                 devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
 143         params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
 144
 145         /* PCI Express */
 146         for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
 147                 if (config->PcieClkSrcUsage[i] == 0)
 148                         config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
 149         }
 150         memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
 151                sizeof(config->PcieClkSrcUsage));
 152         memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
 153                sizeof(config->PcieClkSrcClkReq));
 154
 155         /* eMMC */
 156         params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
 157         if (params->ScsEmmcEnabled) {
 158                 params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
 159                 params->EmmcUseCustomDlls = config->EmmcUseCustomDlls;
 160                 if (config->EmmcUseCustomDlls == 1) {
 161                         params->EmmcTxCmdDelayRegValue =
 162                                         config->EmmcTxCmdDelayRegValue;
 163                         params->EmmcTxDataDelay1RegValue =
 164                                         config->EmmcTxDataDelay1RegValue;
 165                         params->EmmcTxDataDelay2RegValue =
 166                                         config->EmmcTxDataDelay2RegValue;
 167                         params->EmmcRxCmdDataDelay1RegValue =
 168                                         config->EmmcRxCmdDataDelay1RegValue;
 169                         params->EmmcRxCmdDataDelay2RegValue =
 170                                         config->EmmcRxCmdDataDelay2RegValue;
 171                         params->EmmcRxStrobeDelayRegValue =
 172                                         config->EmmcRxStrobeDelayRegValue;
 173                 }
 174         }
 175
 176         /* SD */
 177         params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD);
 178         params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;
 179
 180         params->Heci3Enabled = config->Heci3Enabled;
 181         params->Device4Enable = config->Device4Enable;
 182 }
 183
 184 /* Mainboard GPIO Configuration */
 185 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 186 {
 187         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 188 }