src/soc/intel/broadwell/pch/serialio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <soc/pci_devs.h>
  10 #include <soc/pch.h>
  11 #include <soc/rcba.h>
  12 #include <soc/serialio.h>
  13 #include <soc/intel/broadwell/pch/chip.h>
  14 #include <southbridge/intel/lynxpoint/iobp.h>
  15 #include <types.h>
  16
  17 /* Set D3Hot Power State in ACPI mode */
  18 static void serialio_enable_d3hot(struct resource *res)
  19 {
  20         u32 reg32 = read32(res2mmio(res, PCH_PCS, 0));
  21         reg32 |= PCH_PCS_PS_D3HOT;
  22         write32(res2mmio(res, PCH_PCS, 0), reg32);
  23 }
  24
  25 static bool serialio_uart_is_debug(struct device *dev)
  26 {
  27         if (CONFIG(SERIALIO_UART_CONSOLE)) {
  28                 switch (dev->path.pci.devfn) {
  29                 case PCH_DEVFN_UART0:
  30                         return CONFIG_UART_FOR_CONSOLE == 0;
  31                 case PCH_DEVFN_UART1:
  32                         return CONFIG_UART_FOR_CONSOLE == 1;
  33                 }
  34         }
  35         return false;
  36 }
  37
  38 /* Enable clock in PCI mode */
  39 static void serialio_enable_clock(struct resource *bar0)
  40 {
  41         u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
  42         reg32 |= SIO_REG_PPR_CLOCK_EN;
  43         write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
  44 }
  45
  46 /* Put Serial IO D21:F0-F6 device into desired mode. */
  47 static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode)
  48 {
  49         u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT;
  50
  51         /* Snoop select 1. */
  52         portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1);
  53
  54         /* Set interrupt pin. */
  55         portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin);
  56
  57         if (acpi_mode) {
  58                 /* Enable ACPI interrupt mode. */
  59                 portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN;
  60
  61                 /* Disable PCI config space. */
  62                 portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS;
  63         }
  64
  65         pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl);
  66 }
  67
  68 /* Put Serial IO D23:F0 device into desired mode. */
  69 static void serialio_d23_mode(int acpi_mode)
  70 {
  71         u32 portctrl = 0;
  72
  73         /* Snoop select 1. */
  74         pch_iobp_update(SIO_IOBP_PORTCTRL1, 0,
  75                         SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1));
  76
  77         if (acpi_mode) {
  78                 /* Enable ACPI interrupt mode. */
  79                 portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN;
  80
  81                 /* Disable PCI config space. */
  82                 portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS;
  83         }
  84
  85         pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl);
  86 }
  87
  88 /* Enable LTR Auto Mode for D21:F1-F6. */
  89 static void serialio_d21_ltr(struct resource *bar0)
  90 {
  91         u32 reg;
  92
  93         /* 1. Program BAR0 + 808h[2] = 0b */
  94         reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
  95         reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
  96         write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
  97
  98         /* 2. Program BAR0 + 804h[1:0] = 00b */
  99         reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
 100         reg &= ~SIO_REG_PPR_RST_ASSERT;
 101         write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
 102
 103         /* 3. Program BAR0 + 804h[1:0] = 11b */
 104         reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
 105         reg |= SIO_REG_PPR_RST_ASSERT;
 106         write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
 107
 108         /* 4. Program BAR0 + 814h[31:0] = 00000000h */
 109         write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
 110 }
 111
 112 /* Enable LTR Auto Mode for D23:F0. */
 113 static void serialio_d23_ltr(struct resource *bar0)
 114 {
 115         u32 reg;
 116
 117         /* Program BAR0 + 1008h[2] = 1b */
 118         reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
 119         reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
 120         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
 121
 122         /* Program BAR0 + 1010h = 0x00000000 */
 123         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
 124
 125         /* Program BAR0 + 3Ch[30] = 1b */
 126         reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
 127         reg |= SIO_REG_SDIO_PPR_CMD12_B30;
 128         write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
 129 }
 130
 131 /* Select I2C voltage of 1.8V or 3.3V. */
 132 static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
 133 {
 134         u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
 135         reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
 136         reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
 137         write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
 138 }
 139
 140 /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
 141 static void serialio_init_once(int acpi_mode)
 142 {
 143         if (acpi_mode) {
 144                 /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */
 145                 RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5));
 146         }
 147
 148         /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */
 149         pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f);
 150
 151         /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
 152         pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
 153 }
 154
 155 static void serialio_init(struct device *dev)
 156 {
 157         const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 158         struct resource *bar0, *bar1;
 159         enum pch_acpi_device dev_index = NUM_PCH_ACPI_DEVICES;
 160
 161         printk(BIOS_DEBUG, "Initializing Serial IO device\n");
 162
 163         /* Ensure memory and bus master are enabled */
 164         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 165
 166         /* Find BAR0 and BAR1 */
 167         bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
 168         if (!bar0)
 169                 return;
 170         bar1 = find_resource(dev, PCI_BASE_ADDRESS_1);
 171         if (!bar1)
 172                 return;
 173
 174         if (!config->sio_acpi_mode)
 175                 serialio_enable_clock(bar0);
 176
 177         switch (dev->path.pci.devfn) {
 178         case PCH_DEVFN_SDMA:
 179                 dev_index = PCH_ACPI_SDMA;
 180                 serialio_init_once(config->sio_acpi_mode);
 181                 serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB,
 182                                   config->sio_acpi_mode);
 183                 break;
 184         case PCH_DEVFN_I2C0:
 185                 dev_index = PCH_ACPI_I2C0;
 186                 serialio_d21_ltr(bar0);
 187                 serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
 188                 serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, config->sio_acpi_mode);
 189                 break;
 190         case PCH_DEVFN_I2C1:
 191                 dev_index = PCH_ACPI_I2C1;
 192                 serialio_d21_ltr(bar0);
 193                 serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
 194                 serialio_d21_mode(SIO_ID_I2C1, SIO_PIN_INTC, config->sio_acpi_mode);
 195                 break;
 196         case PCH_DEVFN_SPI0:
 197                 dev_index = PCH_ACPI_GSPI0;
 198                 serialio_d21_ltr(bar0);
 199                 serialio_d21_mode(SIO_ID_SPI0, SIO_PIN_INTC, config->sio_acpi_mode);
 200                 break;
 201         case PCH_DEVFN_SPI1:
 202                 dev_index = PCH_ACPI_GSPI1;
 203                 serialio_d21_ltr(bar0);
 204                 serialio_d21_mode(SIO_ID_SPI1, SIO_PIN_INTC, config->sio_acpi_mode);
 205                 break;
 206         case PCH_DEVFN_UART0:
 207                 dev_index = PCH_ACPI_UART0;
 208                 if (!serialio_uart_is_debug(dev))
 209                         serialio_d21_ltr(bar0);
 210                 serialio_d21_mode(SIO_ID_UART0, SIO_PIN_INTD, config->sio_acpi_mode);
 211                 break;
 212         case PCH_DEVFN_UART1:
 213                 dev_index = PCH_ACPI_UART1;
 214                 if (!serialio_uart_is_debug(dev))
 215                         serialio_d21_ltr(bar0);
 216                 serialio_d21_mode(SIO_ID_UART1, SIO_PIN_INTD, config->sio_acpi_mode);
 217                 break;
 218         case PCH_DEVFN_SDIO:
 219                 dev_index = PCH_ACPI_SDIO;
 220                 serialio_d23_ltr(bar0);
 221                 serialio_d23_mode(config->sio_acpi_mode);
 222                 break;
 223         default:
 224                 return;
 225         }
 226
 227         if (config->sio_acpi_mode) {
 228                 /* Save BAR0 and BAR1 */
 229                 struct pch_acpi_device_state *state = get_acpi_device_state(dev_index);
 230                 state->bar0 = (u32)bar0->base;
 231                 state->bar1 = (u32)bar1->base;
 232
 233                 if (!serialio_uart_is_debug(dev)) {
 234                         /* Do not enable UART if it is used as debug port */
 235                         state->enable = 1;
 236
 237                         /* Put device in D3hot state via BAR1 */
 238                         if (dev->path.pci.devfn != PCH_DEVFN_SDMA)
 239                                 serialio_enable_d3hot(bar1); /* all but SDMA */
 240                 }
 241         }
 242 }
 243
 244 static void serialio_read_resources(struct device *dev)
 245 {
 246         pci_dev_read_resources(dev);
 247
 248         /* Set the configured UART base address for the debug port */
 249         if (CONFIG(SERIALIO_UART_CONSOLE) && serialio_uart_is_debug(dev)) {
 250                 struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
 251                 res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
 252                 res->size = 0x1000;
 253                 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 254         }
 255 }
 256
 257 static struct device_operations device_ops = {
 258         .read_resources         = &serialio_read_resources,
 259         .set_resources          = &pci_dev_set_resources,
 260         .enable_resources       = &pci_dev_enable_resources,
 261         .init                   = &serialio_init,
 262         .ops_pci                = &pci_dev_ops_pci,
 263 };
 264
 265 static const unsigned short pci_device_ids[] = {
 266         0x9c60, 0x9ce0, /* 0:15.0 - SDMA */
 267         0x9c61, 0x9ce1, /* 0:15.1 - I2C0 */
 268         0x9c62, 0x9ce2, /* 0:15.2 - I2C1 */
 269         0x9c65, 0x9ce5, /* 0:15.3 - SPI0 */
 270         0x9c66, 0x9ce6, /* 0:15.4 - SPI1 */
 271         0x9c63, 0x9ce3, /* 0:15.5 - UART0 */
 272         0x9c64, 0x9ce4, /* 0:15.6 - UART1 */
 273         0x9c35, 0x9cb5, /* 0:17.0 - SDIO */
 274         0
 275 };
 276
 277 static const struct pci_driver pch_pcie __pci_driver = {
 278         .ops     = &device_ops,
 279         .vendor  = PCI_VENDOR_ID_INTEL,
 280         .devices = pci_device_ids,
 281 };