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soc/intel/broadwell: Rename `ramstage.h`
[coreboot.git] / src / soc / intel / broadwell / pch / me.c
blob22db6a72f90dff4d5ad6e0f03a6e9dc44e675c55
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 /*
4 * This is a ramstage driver for the Intel Management Engine found in the
5 * southbridge. It handles the required boot-time messages over the
6 * MMIO-based Management Engine Interface to tell the ME that the BIOS is
7 * finished with POST. Additional messages are defined for debug but are
8 * not used unless the console loglevel is high enough.
9 */
10
11 #include <acpi/acpi.h>
12 #include <device/mmio.h>
13 #include <device/pci_ops.h>
14 #include <console/console.h>
15 #include <device/device.h>
16 #include <device/pci.h>
17 #include <device/pci_ids.h>
18 #include <device/pci_def.h>
19 #include <stdlib.h>
20 #include <string.h>
21 #include <delay.h>
22 #include <elog.h>
23 #include <soc/me.h>
24 #include <soc/lpc.h>
25 #include <soc/pch.h>
26 #include <soc/pci_devs.h>
27 #include <soc/rcba.h>
28 #include <soc/intel/broadwell/pch/chip.h>
29
30 #include <vendorcode/google/chromeos/chromeos.h>
31
32 /* Path that the BIOS should take based on ME state */
33 static const char *me_bios_path_values[] = {
34 [ME_NORMAL_BIOS_PATH] = "Normal",
35 [ME_S3WAKE_BIOS_PATH] = "S3 Wake",
36 [ME_ERROR_BIOS_PATH] = "Error",
37 [ME_RECOVERY_BIOS_PATH] = "Recovery",
38 [ME_DISABLE_BIOS_PATH] = "Disable",
39 [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
40 };
41
42 /* MMIO base address for MEI interface */
43 static u8 *mei_base_address;
44
45 static void mei_dump(void *ptr, int dword, int offset, const char *type)
46 {
47 struct mei_csr *csr;
48
49 if (!CONFIG(DEBUG_INTEL_ME))
50 return;
51
52 printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
53
54 switch (offset) {
55 case MEI_H_CSR:
56 case MEI_ME_CSR_HA:
57 csr = ptr;
58 if (!csr) {
59 printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword);
60 break;
61 }
62 printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u "
63 "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth,
64 csr->buffer_read_ptr, csr->buffer_write_ptr,
65 csr->ready, csr->reset, csr->interrupt_generate,
66 csr->interrupt_status, csr->interrupt_enable);
67 break;
68 case MEI_ME_CB_RW:
69 case MEI_H_CB_WW:
70 printk(BIOS_SPEW, "CB: 0x%08x\n", dword);
71 break;
72 default:
73 printk(BIOS_SPEW, "0x%08x\n", offset);
74 break;
75 }
76 }
77
78 /*
79 * ME/MEI access helpers using memcpy to avoid aliasing.
80 */
81
82 static inline void mei_read_dword_ptr(void *ptr, int offset)
83 {
84 u32 dword = read32(mei_base_address + offset);
85 memcpy(ptr, &dword, sizeof(dword));
86 mei_dump(ptr, dword, offset, "READ");
87 }
88
89 static inline void mei_write_dword_ptr(void *ptr, int offset)
90 {
91 u32 dword = 0;
92 memcpy(&dword, ptr, sizeof(dword));
93 write32(mei_base_address + offset, dword);
94 mei_dump(ptr, dword, offset, "WRITE");
95 }
96
97 static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
98 {
99 u32 dword = pci_read_config32(dev, offset);
100 memcpy(ptr, &dword, sizeof(dword));
101 mei_dump(ptr, dword, offset, "PCI READ");
102 }
103
104 static inline void read_host_csr(struct mei_csr *csr)
105 {
106 mei_read_dword_ptr(csr, MEI_H_CSR);
107 }
108
109 static inline void write_host_csr(struct mei_csr *csr)
110 {
111 mei_write_dword_ptr(csr, MEI_H_CSR);
112 }
113
114 static inline void read_me_csr(struct mei_csr *csr)
115 {
116 mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
117 }
118
119 static inline void write_cb(u32 dword)
120 {
121 write32(mei_base_address + MEI_H_CB_WW, dword);
122 mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
123 }
124
125 static inline u32 read_cb(void)
126 {
127 u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
128 mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
129 return dword;
130 }
131
132 /* Wait for ME ready bit to be asserted */
133 static int mei_wait_for_me_ready(void)
134 {
135 struct mei_csr me;
136 unsigned int try = ME_RETRY;
137
138 while (try--) {
139 read_me_csr(&me);
140 if (me.ready)
141 return 0;
142 udelay(ME_DELAY);
143 }
144
145 printk(BIOS_ERR, "ME: failed to become ready\n");
146 return -1;
147 }
148
149 static void mei_reset(void)
150 {
151 struct mei_csr host;
152
153 if (mei_wait_for_me_ready() < 0)
154 return;
155
156 /* Reset host and ME circular buffers for next message */
157 read_host_csr(&host);
158 host.reset = 1;
159 host.interrupt_generate = 1;
160 write_host_csr(&host);
161
162 if (mei_wait_for_me_ready() < 0)
163 return;
164
165 /* Re-init and indicate host is ready */
166 read_host_csr(&host);
167 host.interrupt_generate = 1;
168 host.ready = 1;
169 host.reset = 0;
170 write_host_csr(&host);
171 }
172
173 static int mei_send_packet(struct mei_header *mei, void *req_data)
174 {
175 struct mei_csr host;
176 unsigned int ndata, n;
177 u32 *data;
178
179 /* Number of dwords to write */
180 ndata = mei->length >> 2;
181
182 /* Pad non-dword aligned request message length */
183 if (mei->length & 3)
184 ndata++;
185 if (!ndata) {
186 printk(BIOS_DEBUG, "ME: request has no data\n");
187 return -1;
188 }
189 ndata++; /* Add MEI header */
190
191 /*
192 * Make sure there is still room left in the circular buffer.
193 * Reset the buffer pointers if the requested message will not fit.
194 */
195 read_host_csr(&host);
196 if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
197 printk(BIOS_ERR, "ME: circular buffer full, resetting...\n");
198 mei_reset();
199 read_host_csr(&host);
200 }
201
202 /* Ensure the requested length will fit in the circular buffer. */
203 if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
204 printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n",
205 ndata + 2, host.buffer_depth);
206 return -1;
207 }
208
209 /* Write MEI header */
210 mei_write_dword_ptr(mei, MEI_H_CB_WW);
211 ndata--;
212
213 /* Write message data */
214 data = req_data;
215 for (n = 0; n < ndata; ++n)
216 write_cb(*data++);
217
218 /* Generate interrupt to the ME */
219 read_host_csr(&host);
220 host.interrupt_generate = 1;
221 write_host_csr(&host);
222
223 /* Make sure ME is ready after sending request data */
224 return mei_wait_for_me_ready();
225 }
226
227 static int mei_send_data(u8 me_address, u8 host_address,
228 void *req_data, int req_bytes)
229 {
230 struct mei_header header = {
231 .client_address = me_address,
232 .host_address = host_address,
233 };
234 struct mei_csr host;
235 int current = 0;
236 u8 *req_ptr = req_data;
237
238 while (!header.is_complete) {
239 int remain = req_bytes - current;
240 int buf_len;
241
242 read_host_csr(&host);
243 buf_len = host.buffer_depth - host.buffer_write_ptr;
244
245 if (buf_len > remain) {
246 /* Send all remaining data as final message */
247 header.length = req_bytes - current;
248 header.is_complete = 1;
249 } else {
250 /* Send as much data as the buffer can hold */
251 header.length = buf_len;
252 }
253
254 mei_send_packet(&header, req_ptr);
255
256 req_ptr += header.length;
257 current += header.length;
258 }
259
260 return 0;
261 }
262
263 static int mei_send_header(u8 me_address, u8 host_address,
264 void *header, int header_len, int complete)
265 {
266 struct mei_header mei = {
267 .client_address = me_address,
268 .host_address = host_address,
269 .length = header_len,
270 .is_complete = complete,
271 };
272 return mei_send_packet(&mei, header);
273 }
274
275 static int mei_recv_msg(void *header, int header_bytes,
276 void *rsp_data, int rsp_bytes)
277 {
278 struct mei_header mei_rsp;
279 struct mei_csr me, host;
280 unsigned int ndata, n;
281 unsigned int expected;
282 u32 *data;
283
284 /* Total number of dwords to read from circular buffer */
285 expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2;
286 if (rsp_bytes & 3)
287 expected++;
288
289 if (mei_wait_for_me_ready() < 0)
290 return -1;
291
292 /*
293 * The interrupt status bit does not appear to indicate that the
294 * message has actually been received. Instead we wait until the
295 * expected number of dwords are present in the circular buffer.
296 */
297 for (n = ME_RETRY; n; --n) {
298 read_me_csr(&me);
299 if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
300 break;
301 udelay(ME_DELAY);
302 }
303 if (!n) {
304 printk(BIOS_ERR, "ME: timeout waiting for data: expected "
305 "%u, available %u\n", expected,
306 me.buffer_write_ptr - me.buffer_read_ptr);
307 return -1;
308 }
309
310 /* Read and verify MEI response header from the ME */
311 mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
312 if (!mei_rsp.is_complete) {
313 printk(BIOS_ERR, "ME: response is not complete\n");
314 return -1;
315 }
316
317 /* Handle non-dword responses and expect at least the header */
318 ndata = mei_rsp.length >> 2;
319 if (mei_rsp.length & 3)
320 ndata++;
321 if (ndata != (expected - 1)) {
322 printk(BIOS_ERR, "ME: response is missing data %d != %d\n",
323 ndata, (expected - 1));
324 return -1;
325 }
326
327 /* Read response header from the ME */
328 data = header;
329 for (n = 0; n < (header_bytes >> 2); ++n)
330 *data++ = read_cb();
331 ndata -= header_bytes >> 2;
332
333 /* Make sure caller passed a buffer with enough space */
334 if (ndata != (rsp_bytes >> 2)) {
335 printk(BIOS_ERR, "ME: not enough room in response buffer: "
336 "%u != %u\n", ndata, rsp_bytes >> 2);
337 return -1;
338 }
339
340 /* Read response data from the circular buffer */
341 data = rsp_data;
342 for (n = 0; n < ndata; ++n)
343 *data++ = read_cb();
344
345 /* Tell the ME that we have consumed the response */
346 read_host_csr(&host);
347 host.interrupt_status = 1;
348 host.interrupt_generate = 1;
349 write_host_csr(&host);
350
351 return mei_wait_for_me_ready();
352 }
353
354 static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
355 void *req_data, int req_bytes,
356 void *rsp_data, int rsp_bytes)
357 {
358 struct mkhi_header mkhi_rsp;
359
360 /* Send header */
361 if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS,
362 mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0)
363 return -1;
364
365 /* Send data if available */
366 if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS,
367 req_data, req_bytes) < 0)
368 return -1;
369
370 /* Return now if no response expected */
371 if (!rsp_bytes)
372 return 0;
373
374 /* Read header and data */
375 if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp),
376 rsp_data, rsp_bytes) < 0)
377 return -1;
378
379 if (!mkhi_rsp.is_response ||
380 mkhi->group_id != mkhi_rsp.group_id ||
381 mkhi->command != mkhi_rsp.command) {
382 printk(BIOS_ERR, "ME: invalid response, group %u ?= %u,"
383 "command %u ?= %u, is_response %u\n", mkhi->group_id,
384 mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
385 mkhi_rsp.is_response);
386 return -1;
387 }
388
389 return 0;
390 }
391
392 static inline int mei_sendrecv_icc(struct icc_header *icc,
393 void *req_data, int req_bytes,
394 void *rsp_data, int rsp_bytes)
395 {
396 struct icc_header icc_rsp;
397
398 /* Send header */
399 if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
400 icc, sizeof(*icc), req_bytes ? 0 : 1) < 0)
401 return -1;
402
403 /* Send data if available */
404 if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
405 req_data, req_bytes) < 0)
406 return -1;
407
408 /* Read header and data, if needed */
409 if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp),
410 rsp_data, rsp_bytes) < 0)
411 return -1;
412
413 return 0;
414 }
415
416 /*
417 * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
418 * state machine on the BIOS end doesn't match the ME's state machine.
419 */
420 static void intel_me_mbp_give_up(struct device *dev)
421 {
422 struct mei_csr csr;
423
424 pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP);
425
426 read_host_csr(&csr);
427 csr.reset = 1;
428 csr.interrupt_generate = 1;
429 write_host_csr(&csr);
430 }
431
432 /*
433 * mbp clear routine. This will wait for the ME to indicate that
434 * the MBP has been read and cleared.
435 */
436 static void intel_me_mbp_clear(struct device *dev)
437 {
438 int count;
439 struct me_hfs2 hfs2;
440
441 /* Wait for the mbp_cleared indicator */
442 for (count = ME_RETRY; count > 0; --count) {
443 pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
444 if (hfs2.mbp_cleared)
445 break;
446 udelay(ME_DELAY);
447 }
448
449 if (count == 0) {
450 printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n");
451 intel_me_mbp_give_up(dev);
452 } else {
453 printk(BIOS_INFO, "ME: MBP cleared\n");
454 }
455 }
456
457 static void me_print_fw_version(mbp_fw_version_name *vers_name)
458 {
459 if (!vers_name) {
460 printk(BIOS_ERR, "ME: mbp missing version report\n");
461 return;
462 }
463
464 printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n",
465 vers_name->major_version, vers_name->minor_version,
466 vers_name->hotfix_version, vers_name->build_version);
467 }
468
469 static inline void print_cap(const char *name, int state)
470 {
471 printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
472 name, state ? " en" : "dis");
473 }
474
475 /* Get ME Firmware Capabilities */
476 static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
477 {
478 u32 rule_id = 0;
479 struct me_fwcaps cap_msg;
480 struct mkhi_header mkhi = {
481 .group_id = MKHI_GROUP_ID_FWCAPS,
482 .command = MKHI_FWCAPS_GET_RULE,
483 };
484
485 /* Send request and wait for response */
486 if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32),
487 &cap_msg, sizeof(cap_msg)) < 0) {
488 printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
489 return -1;
490 }
491 *cap = cap_msg.caps_sku;
492 return 0;
493 }
494
495 /* Get ME Firmware Capabilities */
496 static void me_print_fwcaps(mbp_mefwcaps *cap)
497 {
498 mbp_mefwcaps local_caps;
499 if (!cap) {
500 cap = &local_caps;
501 printk(BIOS_ERR, "ME: mbp missing fwcaps report\n");
502 if (mkhi_get_fwcaps(cap))
503 return;
504 }
505
506 print_cap("Full Network manageability", cap->full_net);
507 print_cap("Regular Network manageability", cap->std_net);
508 print_cap("Manageability", cap->manageability);
509 print_cap("IntelR Anti-Theft (AT)", cap->intel_at);
510 print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
511 print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
512 print_cap("ICC Over Clocking", cap->icc_over_clocking);
513 print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
514 print_cap("IPV6", cap->ipv6);
515 print_cap("KVM Remote Control (KVM)", cap->kvm);
516 print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
517 print_cap("Virtual LAN (VLAN)", cap->vlan);
518 print_cap("TLS", cap->tls);
519 print_cap("Wireless LAN (WLAN)", cap->wlan);
520 }
521
522 /* Send END OF POST message to the ME */
523 static int mkhi_end_of_post(void)
524 {
525 struct mkhi_header mkhi = {
526 .group_id = MKHI_GROUP_ID_GEN,
527 .command = MKHI_END_OF_POST,
528 };
529 u32 eop_ack;
530
531 /* Send request and wait for response */
532 if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) {
533 printk(BIOS_ERR, "ME: END OF POST message failed\n");
534 return -1;
535 }
536
537 printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack);
538 return 0;
539 }
540
541 /* Send END OF POST message to the ME */
542 static int mkhi_end_of_post_noack(void)
543 {
544 struct mkhi_header mkhi = {
545 .group_id = MKHI_GROUP_ID_GEN,
546 .command = MKHI_END_OF_POST_NOACK,
547 };
548
549 /* Send request, do not wait for response */
550 if (mei_sendrecv_mkhi(&mkhi, NULL, 0, NULL, 0) < 0) {
551 printk(BIOS_ERR, "ME: END OF POST NOACK message failed\n");
552 return -1;
553 }
554
555 printk(BIOS_INFO, "ME: END OF POST NOACK message successful\n");
556 return 0;
557 }
558
559 /* Send HMRFPO LOCK message to the ME */
560 static int mkhi_hmrfpo_lock(void)
561 {
562 struct mkhi_header mkhi = {
563 .group_id = MKHI_GROUP_ID_HMRFPO,
564 .command = MKHI_HMRFPO_LOCK,
565 };
566 u32 ack;
567
568 /* Send request and wait for response */
569 if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &ack, sizeof(ack)) < 0) {
570 printk(BIOS_ERR, "ME: HMRFPO LOCK message failed\n");
571 return -1;
572 }
573
574 printk(BIOS_INFO, "ME: HMRFPO LOCK message successful (%d)\n", ack);
575 return 0;
576 }
577
578 /* Send HMRFPO LOCK message to the ME, do not wait for response */
579 static int mkhi_hmrfpo_lock_noack(void)
580 {
581 struct mkhi_header mkhi = {
582 .group_id = MKHI_GROUP_ID_HMRFPO,
583 .command = MKHI_HMRFPO_LOCK_NOACK,
584 };
585
586 /* Send request, do not wait for response */
587 if (mei_sendrecv_mkhi(&mkhi, NULL, 0, NULL, 0) < 0) {
588 printk(BIOS_ERR, "ME: HMRFPO LOCK NOACK message failed\n");
589 return -1;
590 }
591
592 printk(BIOS_INFO, "ME: HMRFPO LOCK NOACK message successful\n");
593 return 0;
594 }
595
596 static void intel_me_finalize(struct device *dev)
597 {
598 u16 reg16;
599
600 /* S3 path will have hidden this device already */
601 if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0)
602 return;
603
604 /* Make sure IO is disabled */
605 reg16 = pci_read_config16(dev, PCI_COMMAND);
606 reg16 &= ~(PCI_COMMAND_MASTER |
607 PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
608 pci_write_config16(dev, PCI_COMMAND, reg16);
609
610 /* Hide the PCI device */
611 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
612 RCBA32(FD2);
613 }
614
615 static int me_icc_set_clock_enables(u32 mask)
616 {
617 struct icc_clock_enables_msg clk = {
618 .clock_enables = 0, /* Turn off specified clocks */
619 .clock_mask = mask,
620 .no_response = 1, /* Do not expect response */
621 };
622 struct icc_header icc = {
623 .api_version = ICC_API_VERSION_LYNXPOINT,
624 .icc_command = ICC_SET_CLOCK_ENABLES,
625 .length = sizeof(clk),
626 };
627
628 /* Send request and wait for response */
629 if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
630 printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
631 return -1;
632 }
633 printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
634 return 0;
635 }
636
637 /* Determine the path that we should take based on ME status */
638 static me_bios_path intel_me_path(struct device *dev)
639 {
640 me_bios_path path = ME_DISABLE_BIOS_PATH;
641 struct me_hfs hfs;
642 struct me_hfs2 hfs2;
643
644 /* Check and dump status */
645 intel_me_status();
646
647 pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
648 pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
649
650 /* Check Current Working State */
651 switch (hfs.working_state) {
652 case ME_HFS_CWS_NORMAL:
653 path = ME_NORMAL_BIOS_PATH;
654 break;
655 case ME_HFS_CWS_REC:
656 path = ME_RECOVERY_BIOS_PATH;
657 break;
658 default:
659 path = ME_DISABLE_BIOS_PATH;
660 break;
661 }
662
663 /* Check Current Operation Mode */
664 switch (hfs.operation_mode) {
665 case ME_HFS_MODE_NORMAL:
666 break;
667 case ME_HFS_MODE_DEBUG:
668 case ME_HFS_MODE_DIS:
669 case ME_HFS_MODE_OVER_JMPR:
670 case ME_HFS_MODE_OVER_MEI:
671 default:
672 path = ME_DISABLE_BIOS_PATH;
673 break;
674 }
675
676 /* Check for any error code and valid firmware and MBP */
677 if (hfs.error_code || hfs.fpt_bad)
678 path = ME_ERROR_BIOS_PATH;
679
680 /* Check if the MBP is ready */
681 if (!hfs2.mbp_rdy) {
682 printk(BIOS_CRIT, "%s: mbp is not ready!\n",
683 __func__);
684 path = ME_ERROR_BIOS_PATH;
685 }
686
687 if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) {
688 struct elog_event_data_me_extended data = {
689 .current_working_state = hfs.working_state,
690 .operation_state = hfs.operation_state,
691 .operation_mode = hfs.operation_mode,
692 .error_code = hfs.error_code,
693 .progress_code = hfs2.progress_code,
694 .current_pmevent = hfs2.current_pmevent,
695 .current_state = hfs2.current_state,
696 };
697 elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path);
698 elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT,
699 &data, sizeof(data));
700 }
701
702 return path;
703 }
704
705 /* Prepare ME for MEI messages */
706 static int intel_mei_setup(struct device *dev)
707 {
708 struct resource *res;
709 struct mei_csr host;
710
711 /* Find the MMIO base for the ME interface */
712 res = find_resource(dev, PCI_BASE_ADDRESS_0);
713 if (!res || res->base == 0 || res->size == 0) {
714 printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
715 return -1;
716 }
717 mei_base_address = res2mmio(res, 0, 0);
718
719 /* Ensure Memory and Bus Master bits are set */
720 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
721
722 /* Clean up status for next message */
723 read_host_csr(&host);
724 host.interrupt_generate = 1;
725 host.ready = 1;
726 host.reset = 0;
727 write_host_csr(&host);
728
729 return 0;
730 }
731
732 /* Read the Extend register hash of ME firmware */
733 static int intel_me_extend_valid(struct device *dev)
734 {
735 struct me_heres status;
736 u32 extend[8] = {0};
737 int i, count = 0;
738
739 pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
740 if (!status.extend_feature_present) {
741 printk(BIOS_ERR, "ME: Extend Feature not present\n");
742 return -1;
743 }
744
745 if (!status.extend_reg_valid) {
746 printk(BIOS_ERR, "ME: Extend Register not valid\n");
747 return -1;
748 }
749
750 switch (status.extend_reg_algorithm) {
751 case PCI_ME_EXT_SHA1:
752 count = 5;
753 printk(BIOS_DEBUG, "ME: Extend SHA-1: ");
754 break;
755 case PCI_ME_EXT_SHA256:
756 count = 8;
757 printk(BIOS_DEBUG, "ME: Extend SHA-256: ");
758 break;
759 default:
760 printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n",
761 status.extend_reg_algorithm);
762 return -1;
763 }
764
765 for (i = 0; i < count; ++i) {
766 extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
767 printk(BIOS_DEBUG, "%08x", extend[i]);
768 }
769 printk(BIOS_DEBUG, "\n");
770
771 /* Save hash in NVS for the OS to verify */
772 if (CONFIG(CHROMEOS_NVS))
773 chromeos_set_me_hash(extend, count);
774
775 return 0;
776 }
777
778 static void intel_me_print_mbp(me_bios_payload *mbp_data)
779 {
780 me_print_fw_version(mbp_data->fw_version_name);
781
782 if (CONFIG(DEBUG_INTEL_ME))
783 me_print_fwcaps(mbp_data->fw_capabilities);
784
785 if (mbp_data->plat_time) {
786 printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n",
787 mbp_data->plat_time->wake_event_mrst_time_ms);
788 printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n",
789 mbp_data->plat_time->mrst_pltrst_time_ms);
790 printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n",
791 mbp_data->plat_time->pltrst_cpurst_time_ms);
792 }
793 }
794
795 static u32 me_to_host_words_pending(void)
796 {
797 struct mei_csr me;
798 read_me_csr(&me);
799 if (!me.ready)
800 return 0;
801 return (me.buffer_write_ptr - me.buffer_read_ptr) &
802 (me.buffer_depth - 1);
803 }
804
805 struct mbp_payload {
806 mbp_header header;
807 u32 data[0];
808 };
809
810 /*
811 * Read and print ME MBP data
812 *
813 * Return -1 to indicate a problem (give up)
814 * Return 0 to indicate success (send LOCK+EOP)
815 * Return 1 to indicate success (send LOCK+EOP with NOACK)
816 */
817 static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
818 {
819 mbp_header mbp_hdr;
820 u32 me2host_pending;
821 struct mei_csr host;
822 struct me_hfs2 hfs2;
823 struct mbp_payload *mbp;
824 int i;
825 int ret = 0;
826
827 pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
828
829 if (!hfs2.mbp_rdy) {
830 printk(BIOS_ERR, "ME: MBP not ready\n");
831 intel_me_mbp_give_up(dev);
832 return -1;
833 }
834
835 me2host_pending = me_to_host_words_pending();
836 if (!me2host_pending) {
837 printk(BIOS_ERR, "ME: no mbp data!\n");
838 intel_me_mbp_give_up(dev);
839 return -1;
840 }
841
842 /* we know for sure that at least the header is there */
843 mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW);
844
845 if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) ||
846 (me2host_pending < mbp_hdr.mbp_size)) {
847 printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words"
848 " buffer contains %d words\n",
849 mbp_hdr.num_entries, mbp_hdr.mbp_size,
850 me2host_pending);
851 intel_me_mbp_give_up(dev);
852 return -1;
853 }
854 mbp = malloc(mbp_hdr.mbp_size * sizeof(u32));
855 if (!mbp) {
856 intel_me_mbp_give_up(dev);
857 return -1;
858 }
859
860 mbp->header = mbp_hdr;
861 me2host_pending--;
862
863 i = 0;
864 while (i != me2host_pending) {
865 mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW);
866 i++;
867 }
868
869 read_host_csr(&host);
870
871 /* Check that read and write pointers are equal. */
872 if (host.buffer_read_ptr != host.buffer_write_ptr) {
873 printk(BIOS_INFO, "ME: MBP Read/Write pointer mismatch\n");
874 printk(BIOS_INFO, "ME: MBP Waiting for MBP cleared flag\n");
875
876 /* Tell ME that the host has finished reading the MBP. */
877 host.interrupt_generate = 1;
878 host.reset = 0;
879 write_host_csr(&host);
880
881 /* Wait for the mbp_cleared indicator. */
882 intel_me_mbp_clear(dev);
883 } else {
884 /* Indicate NOACK messages should be used. */
885 ret = 1;
886 }
887
888 /* Dump out the MBP contents. */
889 if (CONFIG(DEBUG_INTEL_ME)) {
890 printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
891 mbp->header.num_entries, mbp->header.mbp_size);
892 for (i = 0; i < mbp->header.mbp_size - 1; i++)
893 printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
894 }
895
896 #define ASSIGN_FIELD_PTR(field_, val_) \
897 { \
898 mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \
899 break; \
900 }
901
902 /* Setup the pointers in the me_bios_payload structure. */
903 for (i = 0; i < mbp->header.mbp_size - 1;) {
904 mbp_item_header *item = (void *)&mbp->data[i];
905
906 switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
907 case MBP_IDENT(KERNEL, FW_VER):
908 ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);
909
910 case MBP_IDENT(ICC, PROFILE):
911 ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]);
912
913 case MBP_IDENT(INTEL_AT, STATE):
914 ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]);
915
916 case MBP_IDENT(KERNEL, FW_CAP):
917 ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]);
918
919 case MBP_IDENT(KERNEL, ROM_BIST):
920 ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]);
921
922 case MBP_IDENT(KERNEL, PLAT_KEY):
923 ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]);
924
925 case MBP_IDENT(KERNEL, FW_TYPE):
926 ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]);
927
928 case MBP_IDENT(KERNEL, MFS_FAILURE):
929 ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]);
930
931 case MBP_IDENT(KERNEL, PLAT_TIME):
932 ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]);
933
934 case MBP_IDENT(NFC, SUPPORT_DATA):
935 ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]);
936 }
937 i += item->length;
938 }
939 #undef ASSIGN_FIELD_PTR
940
941 free(mbp);
942 return ret;
943 }
944
945 /* Check whether ME is present and do basic init */
946 static void intel_me_init(struct device *dev)
947 {
948 const struct soc_intel_broadwell_pch_config *config = config_of(dev);
949 me_bios_path path = intel_me_path(dev);
950 me_bios_payload mbp_data;
951 int mbp_ret;
952 struct me_hfs hfs;
953 struct mei_csr csr;
954
955 /* Do initial setup and determine the BIOS path */
956 printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
957
958 if (path == ME_NORMAL_BIOS_PATH) {
959 /* Validate the extend register */
960 intel_me_extend_valid(dev);
961 }
962
963 memset(&mbp_data, 0, sizeof(mbp_data));
964
965 /*
966 * According to the ME9 BWG, BIOS is required to fetch MBP data in
967 * all boot flows except S3 Resume.
968 */
969
970 /* Prepare MEI MMIO interface */
971 if (intel_mei_setup(dev) < 0)
972 return;
973
974 /* Read ME MBP data */
975 mbp_ret = intel_me_read_mbp(&mbp_data, dev);
976 if (mbp_ret < 0)
977 return;
978 intel_me_print_mbp(&mbp_data);
979
980 /* Set clock enables according to devicetree */
981 if (config->icc_clock_disable)
982 me_icc_set_clock_enables(config->icc_clock_disable);
983
984 /* Make sure ME is in a mode that expects EOP */
985 pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
986
987 /* Abort and leave device alone if not normal mode */
988 if (hfs.fpt_bad ||
989 hfs.working_state != ME_HFS_CWS_NORMAL ||
990 hfs.operation_mode != ME_HFS_MODE_NORMAL)
991 return;
992
993 if (mbp_ret) {
994 /*
995 * MBP Cleared wait is skipped,
996 * Do not expect ACK and reset when complete.
997 */
998
999 /* Send HMRFPO Lock command, no response */
1000 mkhi_hmrfpo_lock_noack();
1001
1002 /* Send END OF POST command, no response */
1003 mkhi_end_of_post_noack();
1004
1005 /* Assert reset and interrupt */
1006 read_host_csr(&csr);
1007 csr.interrupt_generate = 1;
1008 csr.reset = 1;
1009 write_host_csr(&csr);
1010 } else {
1011 /*
1012 * MBP Cleared wait was not skipped
1013 */
1014
1015 /* Send HMRFPO LOCK command */
1016 mkhi_hmrfpo_lock();
1017
1018 /* Send EOP command so ME stops accepting other commands */
1019 mkhi_end_of_post();
1020 }
1021 }
1022
1023 static void intel_me_enable(struct device *dev)
1024 {
1025 /* Avoid talking to the device in S3 path */
1026 if (acpi_is_wakeup_s3()) {
1027 dev->enabled = 0;
1028 pch_disable_devfn(dev);
1029 }
1030 }
1031
1032 static struct device_operations device_ops = {
1033 .read_resources = &pci_dev_read_resources,
1034 .set_resources = &pci_dev_set_resources,
1035 .enable_resources = &pci_dev_enable_resources,
1036 .enable = &intel_me_enable,
1037 .init = &intel_me_init,
1038 .final = &intel_me_finalize,
1039 .ops_pci = &pci_dev_ops_pci,
1040 };
1041
1042 static const unsigned short pci_device_ids[] = {
1043 0x9c3a, /* Low Power */
1044 0x9cba, /* WildcatPoint */
1045 0
1046 };
1047
1048 static const struct pci_driver intel_me __pci_driver = {
1049 .ops = &device_ops,
1050 .vendor = PCI_VENDOR_ID_INTEL,
1051 .devices = pci_device_ids,
1052 };
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